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文件名称:35_OV7725_VGA_DDR3_LX16_joint

  • 所属分类：
  • VHDL编程
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  • 上传时间：
  • 2017-12-18
  • 文件大小：
  • 15.24mb
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  • 0次
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  • 黑色命运****
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多目摄像头同屏显示，实现图像分割，xilinx公司芯片，ISE平台开发(Multi camera on the same screen display, image segmentation, Xilinx company chip, ISE platform development)
相关搜索： ddr3
verilog
vga
屏幕分割

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下载文件列表

文件名大小更新时间
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OV7725_RGB640480_VGA.gise 14179 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OV7725_RGB640480_VGA.xise 42202 2017-11-14
35_OV7725_VGA_DDR3_LX16_joint\par\cmos_ovxxxx_rgb640480.bgn 7806 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\cmos_ovxxxx_rgb640480.bit 464600 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.bld 8663 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.cmd_log 13320 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\cmos_ovxxxx_rgb640480.drc 954 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.lso 6 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ncd 893414 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ngc 944828 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ngd 2019663 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ngr 1020969 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.pad 16959 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.par 33056 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.pcf 365437 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.prj 1234 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ptwx 29893 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.stx
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.syr 373760 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.twr 290813 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.twx 320663 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.unroutes 1380 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.ut 553 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.xpi 45 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480.xst 1195 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_2017-9-22-11-32-4.twx 127153 2017-09-22
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_bitgen.xwbt 321 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_cs.blc 1229 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_cs.ngc 1463097 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_envsettings.html 13308 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_guide.ncd 893414 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_map.map 27595 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_map.mrp 95960 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_map.ncd 515675 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_map.ngm 3520394 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_map.xrpt 57954 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_ngdbuild.xrpt 24650 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_pad.csv 16991 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_pad.txt 68020 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_par.xrpt 201323 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_summary.html 21003 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_summary.xml 409 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_usage.xml 212433 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\CMOS_OVxxxx_RGB640480_xst.xrpt 21129 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\debug.cdc 11673 2017-11-21
35_OV7725_VGA_DDR3_LX16_joint\par\default.xreport 20599 2017-09-21
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\coregen.cgp 238 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\coregen.log 193 2017-09-21
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\create_mig_39_2.tcl 1273 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\edit_mig_39_2.tcl 1124 2017-09-21
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\iseconfig\mig_39_2.projectmgr 5290 2017-09-22
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\iseconfig\mig_39_2.xreport 20671 2017-09-22
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig.prj 3172 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\docs\ug388.pdf 2172724 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\docs\ug416.pdf 80254 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\datasheet.txt 2455 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\log.txt 3646 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\mig.prj 3172 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\create_ise.bat 3266 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\example_top.cdc 13980 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\example_top.ucf 10710 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\icon_coregen.xco 1382 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\ila_coregen.xco 3871 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\ise_flow.bat 4054 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\ise_run.txt 1279 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\makeproj.bat 28 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\mem_interface_top.ut 385 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\readme.txt 6611 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\rem_files.bat 7952 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\set_ise_prop.tcl 5877 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\par\vio_coregen.xco 1570 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\example_top.v 59459 2017-09-17
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\infrastructure.v 10767 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\iodrp_controller.v 11430 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\iodrp_mcb_controller.v 15423 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\mcb_raw_wrapper.v 268315 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\mcb_soft_calibration.v 68316 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\mcb_soft_calibration_top.v 12826 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\mcb_controller\mcb_ui_top.v 113866 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\memc_tb_top.v 86783 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\memc_wrapper.v 66098 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\afifo.v 6916 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\cmd_gen.v 31209 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\cmd_prbs_gen.v 10179 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\data_prbs_gen.v 4609 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v 23611 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\mcb_flow_control.v 17386 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\mcb_traffic_gen.v 26135 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\rd_data_gen.v 11021 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\read_data_path.v 16822 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\read_posted_fifo.v 8119 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\sp6_data_gen.v 27751 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\tg_status.v 4732 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\v6_data_gen.v 122967 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\write_data_path.v 5755 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\rtl\traffic_gen\wr_data_gen.v 11286 2013-10-14
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\sim\functional\ddr.cr.mti 2 2017-09-24
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\sim\functional\ddr.mpf 78681 2017-09-20
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\sim\functional\DDR3.cr.mti 2 2017-09-25
35_OV7725_VGA_DDR3_LX16_joint\par\ipcore_dir\mig_39_2\mig_39_2\example_design\sim\functional\DDR3.mpf 94975 2017-09-20

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