文件名称:ModularDesign
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一个简单的Modular Design设计,源代码,分别用Verilog和VHDL两种语言描述,本设计顶层模块由3个子模块组成.
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下载文件列表
压缩包 : 83390044modulardesign.rar 列表 Modular_Design\Imp_modules\module_a\module_a.cel Modular_Design\Imp_modules\module_a\module_a.edf Modular_Design\Imp_modules\module_a\module_a.ngo Modular_Design\Imp_modules\module_a\module_a.ucf Modular_Design\Imp_modules\module_a\netlist.lst Modular_Design\Imp_modules\module_a\top.bld Modular_Design\Imp_modules\module_a\top.mrp Modular_Design\Imp_modules\module_a\top.ncd Modular_Design\Imp_modules\module_a\top.ngd Modular_Design\Imp_modules\module_a\top.ngm Modular_Design\Imp_modules\module_a\top.ngo Modular_Design\Imp_modules\module_a\top.pcf Modular_Design\Imp_modules\module_a\top_ngdbuild.nav Modular_Design\Imp_modules\module_a\top_routed.dly Modular_Design\Imp_modules\module_a\top_routed.ncd Modular_Design\Imp_modules\module_a\top_routed.pad Modular_Design\Imp_modules\module_a\top_routed.par Modular_Design\Imp_modules\module_a\top_routed.twr Modular_Design\Imp_modules\module_a\top_routed.xpi Modular_Design\Imp_modules\module_b\module_b.ngc Modular_Design\Imp_modules\module_b\module_b.ucf Modular_Design\Imp_modules\module_b\netlist.lst Modular_Design\Imp_modules\module_b\top.bld Modular_Design\Imp_modules\module_b\top.mrp Modular_Design\Imp_modules\module_b\top.ncd Modular_Design\Imp_modules\module_b\top.ngd Modular_Design\Imp_modules\module_b\top.ngm Modular_Design\Imp_modules\module_b\top.ngo Modular_Design\Imp_modules\module_b\top.pcf Modular_Design\Imp_modules\module_b\top_ngdbuild.nav Modular_Design\Imp_modules\module_b\top_routed.dly Modular_Design\Imp_modules\module_b\top_routed.ncd Modular_Design\Imp_modules\module_b\top_routed.pad Modular_Design\Imp_modules\module_b\top_routed.par Modular_Design\Imp_modules\module_b\top_routed.twr Modular_Design\Imp_modules\module_b\top_routed.xpi Modular_Design\Imp_modules\module_c\module_c.edf Modular_Design\Imp_modules\module_c\module_c.ngo Modular_Design\Imp_modules\module_c\module_c.ucf Modular_Design\Imp_modules\module_c\netlist.lst Modular_Design\Imp_modules\module_c\top.bld Modular_Design\Imp_modules\module_c\top.mrp Modular_Design\Imp_modules\module_c\top.ncd Modular_Design\Imp_modules\module_c\top.ngd Modular_Design\Imp_modules\module_c\top.ngm Modular_Design\Imp_modules\module_c\top.ngo Modular_Design\Imp_modules\module_c\top.pcf Modular_Design\Imp_modules\module_c\top_ngdbuild.nav Modular_Design\Imp_modules\module_c\top_routed.dly Modular_Design\Imp_modules\module_c\top_routed.ncd Modular_Design\Imp_modules\module_c\top_routed.pad Modular_Design\Imp_modules\module_c\top_routed.par Modular_Design\Imp_modules\module_c\top_routed.twr Modular_Design\Imp_modules\module_c\top_routed.xpi Modular_Design\Imp_top\netlist.lst Modular_Design\Imp_top\ngd2ver.log Modular_Design\Imp_top\ngd2vhdl.log Modular_Design\Imp_top\top.alf Modular_Design\Imp_top\top.bld Modular_Design\Imp_top\top.cel Modular_Design\Imp_top\top.edf Modular_Design\Imp_top\top.fnf Modular_Design\Imp_top\top.mrp Modular_Design\Imp_top\top.ncd Modular_Design\Imp_top\top.nga Modular_Design\Imp_top\top.ngd Modular_Design\Imp_top\top.ngm Modular_Design\Imp_top\top.ngo Modular_Design\Imp_top\top.pcf Modular_Design\Imp_top\top.sdf Modular_Design\Imp_top\top.ucf Modular_Design\Imp_top\top.v Modular_Design\Imp_top\top.vhd Modular_Design\Imp_top\top_constraints.ucf Modular_Design\Imp_top\top_ngdbuild.nav Modular_Design\Imp_top\top_routed.dly Modular_Design\Imp_top\top_routed.grf Modular_Design\Imp_top\top_routed.ncd Modular_Design\Imp_top\top_routed.pad Modular_Design\Imp_top\top_routed.par Modular_Design\Imp_top\top_routed.twr Modular_Design\Imp_top\top_routed.xpi Modular_Design\Imp_top\_fplan.ucf Modular_Design\PIMs\module_a\module_a.ncd Modular_Design\PIMs\module_a\module_a.ngc Modular_Design\PIMs\module_a\module_a.ngm Modular_Design\PIMs\module_a\top.ngc Modular_Design\PIMs\module_b\module_b.ncd Modular_Design\PIMs\module_b\module_b.ngc Modular_Design\PIMs\module_b\module_b.ngm Modular_Design\PIMs\module_b\top.ngc Modular_Design\PIMs\module_c\module_c.ncd Modular_Design\PIMs\module_c\module_c.ngc Modular_Design\PIMs\module_c\module_c.ngm Modular_Design\PIMs\module_c\top.ngc Modular_Design\syn_modules\module_a\module_a.v Modular_Design\syn_modules\module_a\rev_1\module_a.edf Modular_Design\syn_modules\module_a\rev_1\module_a.fse Modular_Design\syn_modules\module_a\rev_1\module_a.ncf Modular_Design\syn_modules\module_a\rev_1\module_a.plg Modular_Design\syn_modules\module_a\rev_1\module_a.srd Modular_Design\syn_modules\module_a\rev_1\module_a.srm Modular_Design\syn_modules\module_a\rev_1\module_a.srr Modular_Design\syn_modules\module_a\rev_1\module_a.srs Modular_Design\syn_modules\module_a\rev_1\module_a.tlg Modular_Design\syn_modules\module_a\SynPro_module_a.prd Modular_Design\syn_modules\module_a\SynPro_module_a.prj Modular_Design\syn_modules\module_b\module_b.v Modular_Design\syn_modules\module_b\XST_module_b\automake.log Modular_Design\syn_modules\module_b\XST_module_b\module_b.ana Modular_Design\syn_modules\module_b\XST_module_b\module_b.cmd_log Modular_Design\syn_modules\module_b\XST_module_b\module_b.jhd Modular_Design\syn_modules\module_b\XST_module_b\module_b.ngc Modular_Design\syn_modules\module_b\XST_module_b\module_b.ngr Modular_Design\syn_modules\module_b\XST_module_b\module_b.prj Modular_Design\syn_modules\module_b\XST_module_b\module_b.sprj Modular_Design\syn_modules\module_b\XST_module_b\module_b.stx Modular_Design\syn_modules\module_b\XST_module_b\module_b.syr Modular_Design\syn_modules\module_b\XST_module_b\XST_module_b.npl Modular_Design\syn_modules\module_b\XST_module_b\XST_module_b.ptf Modular_Design\syn_modules\module_b\XST_module_b\__projnav\module_b.xst Modular_Design\syn_modules\module_b\XST_module_b\__projnav\module_b._prj Modular_Design\syn_modules\module_b\XST_module_b\__projnav\module_b._sprj Modular_Design\syn_modules\module_b\XST_module_b\__projnav\module_b_jhdparse_tcl.rsp Modular_Design\syn_modules\module_b\XST_module_b\__projnav\runXst_tcl.rsp Modular_Design\syn_modules\module_b\XST_module_b\__projnav\xst_module_b.gfl Modular_Design\syn_modules\module_b\XST_module_b\__projnav\xst_module_b_flowplus.gfl Modular_Design\syn_modules\module_b\XST_module_b\__projnav.log Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c\module_c.cst Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c\module_c.rpt Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c\module_c.ws Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c-Optimized\module_c-Optimized.cst Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c-Optimized\module_c-Optimized.rpt Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c-Optimized\module_c-Optimized.ws Modular_Design\syn_modules\module_c\FE_module_c\FE_module_c.exp Modular_Design\syn_modules\module_c\FE_module_c\files\L1.rpt Modular_Design\syn_modules\module_c\FE_module_c\module_c.edf Modular_Design\syn_modules\module_c\FE_module_c\module_c.ncf Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\Anal.info Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\Anal.out Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\module_c%verilog.syn Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\module_c%verilog__verilog.syn Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\module_c.hnl Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\MODULE_C.mra Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\module_c.out Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK\module_c.sts Modular_Design\syn_modules\module_c\module_c.v Modular_Design\syn_top\rev_1\top.edf Modular_Design\syn_top\rev_1\top.fse Modular_Design\syn_top\rev_1\top.ncf Modular_Design\syn_top\rev_1\top.plg Modular_Design\syn_top\rev_1\top.srd Modular_Design\syn_top\rev_1\top.srm Modular_Design\syn_top\rev_1\top.srr Modular_Design\syn_top\rev_1\top.srs Modular_Design\syn_top\rev_1\top.tlg Modular_Design\syn_top\SynPro_top.prd Modular_Design\syn_top\SynPro_top.prj Modular_Design\syn_top\top.v Modular_Design\syn_top\virtex2.v source\vhdl\module_a.vhd source\vhdl\module_b.vhd source\vhdl\module_c.vhd source\vhdl\top.vhd source\vhdl\virtex2.vhd source\vlog\module_a.v source\vlog\module_b.v source\vlog\module_c.v source\vlog\top.v source\vlog\virtex2.v Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c Modular_Design\syn_modules\module_c\FE_module_c\chips\module_c-Optimized Modular_Design\syn_modules\module_c\FE_module_c\workdirs\WORK Modular_Design\syn_modules\module_b\XST_module_b\__projnav Modular_Design\syn_modules\module_c\FE_module_c\chips Modular_Design\syn_modules\module_c\FE_module_c\files Modular_Design\syn_modules\module_c\FE_module_c\workdirs Modular_Design\syn_modules\module_a\rev_1 Modular_Design\syn_modules\module_b\XST_module_b Modular_Design\syn_modules\module_c\FE_module_c Modular_Design\Imp_modules\module_a Modular_Design\Imp_modules\module_b Modular_Design\Imp_modules\module_c Modular_Design\PIMs\module_a Modular_Design\PIMs\module_b Modular_Design\PIMs\module_c Modular_Design\syn_modules\module_a Modular_Design\syn_modules\module_b Modular_Design\syn_modules\module_c Modular_Design\syn_top\rev_1 Modular_Design\Imp_modules Modular_Design\Imp_top Modular_Design\PIMs Modular_Design\syn_modules Modular_Design\syn_top source\vhdl source\vlog Modular_Design source