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文件名称:2_FPGA_Modbus_1M_RAM

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  • 其他小程序
  • 资源属性：
  • [Windows] [Visual.Net] [源码]
  • 上传时间：
  • 2017-10-31
  • 文件大小：
  • 1.61mb
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  • 0次
  • 提 供 者：
  • Darr*****
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修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

用 FPGA 编写的 MODBUS 协议通信(Communication of MODBUS protocol written with FPGA)
相关搜索： FPGA
编写的
MODBUS
modbus

(系统自动生成,下载前可以参看下载内容)

下载文件列表

2_FPGA_Modbus_1M_RAM

2_FPGA_Modbus_1M_RAM\FPGA_Modbus

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Modelsim

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.asm.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.done

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.dpf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.fit.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.fit.smsg

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.fit.summary

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.flow.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.jdi

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.map.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.map.smsg

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.map.summary

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.merge.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.pin

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.pof

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.qpf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.qsf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.qws

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.sof

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.tan.rpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\TOP_Module.tan.summary

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\db

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\db\TOP_Module.db_info

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\db\TOP_Module.eco.cdb

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\README

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.atm

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.dfp

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.hdbx

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.kpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.logdb

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.cmp.rcf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.map.atm

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.map.dpi

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.map.hdbx

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.map.kpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.root_partition.merge_hb.atm

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Quartus\incremental_db\compiled_partitions\TOP_Module.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\Testbench

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\CONTROL_Module.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\CONTROL_Module.v.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\MODBUS_Module.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\MODBUS_Module.v.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M.bsf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M.ppf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M.qip

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M_inst.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M_wave0.jpg

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\PLL_CLK_10M_waveforms.html

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM.bsf

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM.qip

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_ADD_DATA.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_ADD_DATA.v.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_INIT.mif

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_INIT.mif.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_bb.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_inst.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_wave0.jpg

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_wave1.jpg

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\RAM_waveforms.html

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\TEST.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\TEST.v.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\TOP_Module.v

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\TOP_Module.v.bak

2_FPGA_Modbus_1M_RAM\FPGA_Modbus\src\UART.v

2_FPGA_Modbus_1M_RAM\Modbus Poll

2_FPGA_Modbus_1M_RAM\Modbus Poll\005.reg

2_FPGA_Modbus_1M_RAM\Modbus Poll\MBPOLL.HLP

2_FPGA_Modbus_1M_RAM\Modbus Poll\ReadMe.txt

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VB6

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VB6\vbexample.frm

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VB6\vbexample.vbp

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VB6\vbexample.vbw

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET\VBExample.resX

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET\VBExample.vb

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET\vbexample.sln

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET\vbexample.vbproj

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\VBNET\vbexample.vbproj.user

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\excel

2_FPGA_Modbus_1M_RAM\Modbus Poll\examples\excel\example.xls

2_FPGA_Modbus_1M_RAM\Modbus Poll\license.txt

2_FPGA_Modbus_1M_RAM\Modbus Poll\mbpoll.GID

2_FPGA_Modbus_1M_RAM\Modbus Poll\mbpoll.exe

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