文件名称:MIL-STD-1553B代码
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FPGA实现1553B编解码器功能 Verilog语言(FPGA implementation of 1553B codec function, Verilog language)
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下载文件列表
1553_enc_dec\1553_enc_dec.asm.rpt
1553_enc_dec\1553_enc_dec.bdf
1553_enc_dec\1553_enc_dec.done
1553_enc_dec\1553_enc_dec.fit.eqn
1553_enc_dec\1553_enc_dec.fit.rpt
1553_enc_dec\1553_enc_dec.fit.smsg
1553_enc_dec\1553_enc_dec.fit.summary
1553_enc_dec\1553_enc_dec.flow.rpt
1553_enc_dec\1553_enc_dec.map.eqn
1553_enc_dec\1553_enc_dec.map.rpt
1553_enc_dec\1553_enc_dec.map.summary
1553_enc_dec\1553_enc_dec.pin
1553_enc_dec\1553_enc_dec.pof
1553_enc_dec\1553_enc_dec.qpf
1553_enc_dec\1553_enc_dec.qsf
1553_enc_dec\1553_enc_dec.qws
1553_enc_dec\1553_enc_dec.sim.rpt
1553_enc_dec\1553_enc_dec.sof
1553_enc_dec\1553_enc_dec.tan.rpt
1553_enc_dec\1553_enc_dec.tan.summary
1553_enc_dec\1553_enc_dec.vwf
1553_enc_dec\1553_enc_dec_assignment_defaults.qdf
1553_enc_dec\cmp_state.ini
1553_enc_dec\db\1553_enc_dec.db_info
1553_enc_dec\db\1553_enc_dec.eco.cdb
1553_enc_dec\db\1553_enc_dec.sim.cvwf
1553_enc_dec\db\1553_enc_dec.sim.vwf
1553_enc_dec\db\1553_enc_dec.sld_design_entry.sci
1553_enc_dec\db\1553_enc_dec_cmp.qrpt
1553_enc_dec\db\1553_enc_dec_sim.qrpt
1553_enc_dec\db\cntr_e18.tdf
1553_enc_dec\db\cntr_m08.tdf
1553_enc_dec\db\prev_cmp_1553_enc_dec.qmsg
1553_enc_dec\db\wed.wsf
1553_enc_dec\decoder_1553.v
1553_enc_dec\docs\rd1021.pdf
1553_enc_dec\docs\readme.txt
1553_enc_dec\encoder_1553.v
1553_enc_dec\incremental_db\compiled_partitions\1553_enc_dec.root_partition.map.kpt
1553_enc_dec\incremental_db\README
1553_enc_dec\par\EC\decoder_1553.prf
1553_enc_dec\par\EC\decoder_1553.syn
1553_enc_dec\par\EC\encoder_1553.prf
1553_enc_dec\par\EC\encoder_1553.syn
1553_enc_dec\sim.cfg
1553_enc_dec\simulation\EC\scripts\runsim_1553.do
1553_enc_dec\source\decoder_1553.v
1553_enc_dec\source\encoder_1553.v
1553_enc_dec\synthesis\EC\synplify\decoder_1553.prj
1553_enc_dec\synthesis\EC\synplify\decoder_1553.sdc
1553_enc_dec\synthesis\EC\synplify\encoder_1553.prj
1553_enc_dec\synthesis\EC\synplify\encoder_1553.sdc
1553_enc_dec\testbench\test_1553.v
1553_enc_dec\tests\readme.txt
1553_enc_dec\undo_redo.txt
1553_enc_dec\simulation\EC\scripts
1553_enc_dec\synthesis\EC\synplify
1553_enc_dec\incremental_db\compiled_partitions
1553_enc_dec\par\EC
1553_enc_dec\simulation\EC
1553_enc_dec\synthesis\EC
1553_enc_dec\db
1553_enc_dec\docs
1553_enc_dec\incremental_db
1553_enc_dec\par
1553_enc_dec\simulation
1553_enc_dec\source
1553_enc_dec\synthesis
1553_enc_dec\testbench
1553_enc_dec\tests
1553_enc_dec
1553_enc_dec\1553_enc_dec.bdf
1553_enc_dec\1553_enc_dec.done
1553_enc_dec\1553_enc_dec.fit.eqn
1553_enc_dec\1553_enc_dec.fit.rpt
1553_enc_dec\1553_enc_dec.fit.smsg
1553_enc_dec\1553_enc_dec.fit.summary
1553_enc_dec\1553_enc_dec.flow.rpt
1553_enc_dec\1553_enc_dec.map.eqn
1553_enc_dec\1553_enc_dec.map.rpt
1553_enc_dec\1553_enc_dec.map.summary
1553_enc_dec\1553_enc_dec.pin
1553_enc_dec\1553_enc_dec.pof
1553_enc_dec\1553_enc_dec.qpf
1553_enc_dec\1553_enc_dec.qsf
1553_enc_dec\1553_enc_dec.qws
1553_enc_dec\1553_enc_dec.sim.rpt
1553_enc_dec\1553_enc_dec.sof
1553_enc_dec\1553_enc_dec.tan.rpt
1553_enc_dec\1553_enc_dec.tan.summary
1553_enc_dec\1553_enc_dec.vwf
1553_enc_dec\1553_enc_dec_assignment_defaults.qdf
1553_enc_dec\cmp_state.ini
1553_enc_dec\db\1553_enc_dec.db_info
1553_enc_dec\db\1553_enc_dec.eco.cdb
1553_enc_dec\db\1553_enc_dec.sim.cvwf
1553_enc_dec\db\1553_enc_dec.sim.vwf
1553_enc_dec\db\1553_enc_dec.sld_design_entry.sci
1553_enc_dec\db\1553_enc_dec_cmp.qrpt
1553_enc_dec\db\1553_enc_dec_sim.qrpt
1553_enc_dec\db\cntr_e18.tdf
1553_enc_dec\db\cntr_m08.tdf
1553_enc_dec\db\prev_cmp_1553_enc_dec.qmsg
1553_enc_dec\db\wed.wsf
1553_enc_dec\decoder_1553.v
1553_enc_dec\docs\rd1021.pdf
1553_enc_dec\docs\readme.txt
1553_enc_dec\encoder_1553.v
1553_enc_dec\incremental_db\compiled_partitions\1553_enc_dec.root_partition.map.kpt
1553_enc_dec\incremental_db\README
1553_enc_dec\par\EC\decoder_1553.prf
1553_enc_dec\par\EC\decoder_1553.syn
1553_enc_dec\par\EC\encoder_1553.prf
1553_enc_dec\par\EC\encoder_1553.syn
1553_enc_dec\sim.cfg
1553_enc_dec\simulation\EC\scripts\runsim_1553.do
1553_enc_dec\source\decoder_1553.v
1553_enc_dec\source\encoder_1553.v
1553_enc_dec\synthesis\EC\synplify\decoder_1553.prj
1553_enc_dec\synthesis\EC\synplify\decoder_1553.sdc
1553_enc_dec\synthesis\EC\synplify\encoder_1553.prj
1553_enc_dec\synthesis\EC\synplify\encoder_1553.sdc
1553_enc_dec\testbench\test_1553.v
1553_enc_dec\tests\readme.txt
1553_enc_dec\undo_redo.txt
1553_enc_dec\simulation\EC\scripts
1553_enc_dec\synthesis\EC\synplify
1553_enc_dec\incremental_db\compiled_partitions
1553_enc_dec\par\EC
1553_enc_dec\simulation\EC
1553_enc_dec\synthesis\EC
1553_enc_dec\db
1553_enc_dec\docs
1553_enc_dec\incremental_db
1553_enc_dec\par
1553_enc_dec\simulation
1553_enc_dec\source
1553_enc_dec\synthesis
1553_enc_dec\testbench
1553_enc_dec\tests
1553_enc_dec