文件名称:等精度数字频率计
介绍说明－－下载内容均来自于网络，请自行研究使用
可以测量1HZ-150MHZ矩形波(其他波形需整形后输入)信号，误差<0.01%，串口输出NC和NX值。(1HZ-150MHZ square wave can be measured (other waveform needs to be shaped after the input) signal, error <0.01%, serial output NC and NX values.)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Verilog_MyTest
Verilog_MyTest\.qsys_edit
Verilog_MyTest\.qsys_edit\filters.xml
Verilog_MyTest\.qsys_edit\preferences.xml
Verilog_MyTest\PLL_300m.ppf
Verilog_MyTest\PLL_300m.qip
Verilog_MyTest\PLL_300m.v
Verilog_MyTest\PLL_300m_bb.v
Verilog_MyTest\PLL_300m_inst.v
Verilog_MyTest\PLL_inst.ppf
Verilog_MyTest\PLL_inst.qip
Verilog_MyTest\PLL_inst.v
Verilog_MyTest\PLL_inst_bb.v
Verilog_MyTest\PLL_inst_inst.v
Verilog_MyTest\Verilog1.v
Verilog_MyTest\Verilog1.v.bak
Verilog_MyTest\Verilog_MyTest.qpf
Verilog_MyTest\Verilog_MyTest.qsf
Verilog_MyTest\Verilog_MyTest.qws
Verilog_MyTest\Verilog_MyTest.tis_db_list.ddb
Verilog_MyTest\Verilog_MyTest.v
Verilog_MyTest\Verilog_MyTest.v.bak
Verilog_MyTest\Verilog_MyTest_assignment_defaults.qdf
Verilog_MyTest\Verilog_MyTest_nativelink_simulation.rpt
Verilog_MyTest\db
Verilog_MyTest\db\.cmp.kpt
Verilog_MyTest\db\PLL_300m_altpll.v
Verilog_MyTest\db\PLL_300m_altpll1.v
Verilog_MyTest\db\PLL_300m_altpll2.v
Verilog_MyTest\db\Verilog_MyTest.db_info
Verilog_MyTest\db\Verilog_MyTest.sld_design_entry.sci
Verilog_MyTest\db\Verilog_MyTest_partition_pins.json
Verilog_MyTest\db\add_sub_7pc.tdf
Verilog_MyTest\db\add_sub_8pc.tdf
Verilog_MyTest\db\alt_u_div_07f.tdf
Verilog_MyTest\db\alt_u_div_0af.tdf
Verilog_MyTest\db\alt_u_div_0bf.tdf
Verilog_MyTest\db\alt_u_div_1af.tdf
Verilog_MyTest\db\alt_u_div_1bf.tdf
Verilog_MyTest\db\alt_u_div_27f.tdf
Verilog_MyTest\db\alt_u_div_2af.tdf
Verilog_MyTest\db\alt_u_div_2bf.tdf
Verilog_MyTest\db\alt_u_div_3af.tdf
Verilog_MyTest\db\alt_u_div_3bf.tdf
Verilog_MyTest\db\alt_u_div_47f.tdf
Verilog_MyTest\db\alt_u_div_4af.tdf
Verilog_MyTest\db\alt_u_div_4bf.tdf
Verilog_MyTest\db\alt_u_div_57f.tdf
Verilog_MyTest\db\alt_u_div_5af.tdf
Verilog_MyTest\db\alt_u_div_5bf.tdf
Verilog_MyTest\db\alt_u_div_67f.tdf
Verilog_MyTest\db\alt_u_div_6af.tdf
Verilog_MyTest\db\alt_u_div_6bf.tdf
Verilog_MyTest\db\alt_u_div_77f.tdf
Verilog_MyTest\db\alt_u_div_7af.tdf
Verilog_MyTest\db\alt_u_div_7bf.tdf
Verilog_MyTest\db\alt_u_div_84f.tdf
Verilog_MyTest\db\alt_u_div_8af.tdf
Verilog_MyTest\db\alt_u_div_8bf.tdf
Verilog_MyTest\db\alt_u_div_9af.tdf
Verilog_MyTest\db\alt_u_div_9bf.tdf
Verilog_MyTest\db\alt_u_div_a7f.tdf
Verilog_MyTest\db\alt_u_div_aaf.tdf
Verilog_MyTest\db\alt_u_div_abf.tdf
Verilog_MyTest\db\alt_u_div_b7f.tdf
Verilog_MyTest\db\alt_u_div_baf.tdf
Verilog_MyTest\db\alt_u_div_bbf.tdf
Verilog_MyTest\db\alt_u_div_c7f.tdf
Verilog_MyTest\db\alt_u_div_caf.tdf
Verilog_MyTest\db\alt_u_div_cbf.tdf
Verilog_MyTest\db\alt_u_div_d7f.tdf
Verilog_MyTest\db\alt_u_div_daf.tdf
Verilog_MyTest\db\alt_u_div_dbf.tdf
Verilog_MyTest\db\alt_u_div_e7f.tdf
Verilog_MyTest\db\alt_u_div_eaf.tdf
Verilog_MyTest\db\alt_u_div_ebf.tdf
Verilog_MyTest\db\alt_u_div_f7f.tdf
Verilog_MyTest\db\alt_u_div_faf.tdf
Verilog_MyTest\db\alt_u_div_fbf.tdf
Verilog_MyTest\db\alt_u_div_g7f.tdf
Verilog_MyTest\db\alt_u_div_gaf.tdf
Verilog_MyTest\db\alt_u_div_gbf.tdf
Verilog_MyTest\db\alt_u_div_h7f.tdf
Verilog_MyTest\db\alt_u_div_haf.tdf
Verilog_MyTest\db\alt_u_div_hbf.tdf
Verilog_MyTest\db\alt_u_div_i7f.tdf
Verilog_MyTest\db\alt_u_div_iaf.tdf
Verilog_MyTest\db\alt_u_div_j7f.tdf
Verilog_MyTest\db\alt_u_div_jaf.tdf
Verilog_MyTest\db\alt_u_div_k7f.tdf
Verilog_MyTest\db\alt_u_div_kaf.tdf
Verilog_MyTest\db\alt_u_div_l7f.tdf
Verilog_MyTest\db\alt_u_div_laf.tdf
Verilog_MyTest\db\alt_u_div_m7f.tdf
Verilog_MyTest\db\alt_u_div_maf.tdf
Verilog_MyTest\db\alt_u_div_n7f.tdf
Verilog_MyTest\db\alt_u_div_naf.tdf
Verilog_MyTest\db\alt_u_div_o7f.tdf
Verilog_MyTest\db\alt_u_div_oaf.tdf
Verilog_MyTest\db\alt_u_div_paf.tdf
Verilog_MyTest\.qsys_edit
Verilog_MyTest\.qsys_edit\filters.xml
Verilog_MyTest\.qsys_edit\preferences.xml
Verilog_MyTest\PLL_300m.ppf
Verilog_MyTest\PLL_300m.qip
Verilog_MyTest\PLL_300m.v
Verilog_MyTest\PLL_300m_bb.v
Verilog_MyTest\PLL_300m_inst.v
Verilog_MyTest\PLL_inst.ppf
Verilog_MyTest\PLL_inst.qip
Verilog_MyTest\PLL_inst.v
Verilog_MyTest\PLL_inst_bb.v
Verilog_MyTest\PLL_inst_inst.v
Verilog_MyTest\Verilog1.v
Verilog_MyTest\Verilog1.v.bak
Verilog_MyTest\Verilog_MyTest.qpf
Verilog_MyTest\Verilog_MyTest.qsf
Verilog_MyTest\Verilog_MyTest.qws
Verilog_MyTest\Verilog_MyTest.tis_db_list.ddb
Verilog_MyTest\Verilog_MyTest.v
Verilog_MyTest\Verilog_MyTest.v.bak
Verilog_MyTest\Verilog_MyTest_assignment_defaults.qdf
Verilog_MyTest\Verilog_MyTest_nativelink_simulation.rpt
Verilog_MyTest\db
Verilog_MyTest\db\.cmp.kpt
Verilog_MyTest\db\PLL_300m_altpll.v
Verilog_MyTest\db\PLL_300m_altpll1.v
Verilog_MyTest\db\PLL_300m_altpll2.v
Verilog_MyTest\db\Verilog_MyTest.db_info
Verilog_MyTest\db\Verilog_MyTest.sld_design_entry.sci
Verilog_MyTest\db\Verilog_MyTest_partition_pins.json
Verilog_MyTest\db\add_sub_7pc.tdf
Verilog_MyTest\db\add_sub_8pc.tdf
Verilog_MyTest\db\alt_u_div_07f.tdf
Verilog_MyTest\db\alt_u_div_0af.tdf
Verilog_MyTest\db\alt_u_div_0bf.tdf
Verilog_MyTest\db\alt_u_div_1af.tdf
Verilog_MyTest\db\alt_u_div_1bf.tdf
Verilog_MyTest\db\alt_u_div_27f.tdf
Verilog_MyTest\db\alt_u_div_2af.tdf
Verilog_MyTest\db\alt_u_div_2bf.tdf
Verilog_MyTest\db\alt_u_div_3af.tdf
Verilog_MyTest\db\alt_u_div_3bf.tdf
Verilog_MyTest\db\alt_u_div_47f.tdf
Verilog_MyTest\db\alt_u_div_4af.tdf
Verilog_MyTest\db\alt_u_div_4bf.tdf
Verilog_MyTest\db\alt_u_div_57f.tdf
Verilog_MyTest\db\alt_u_div_5af.tdf
Verilog_MyTest\db\alt_u_div_5bf.tdf
Verilog_MyTest\db\alt_u_div_67f.tdf
Verilog_MyTest\db\alt_u_div_6af.tdf
Verilog_MyTest\db\alt_u_div_6bf.tdf
Verilog_MyTest\db\alt_u_div_77f.tdf
Verilog_MyTest\db\alt_u_div_7af.tdf
Verilog_MyTest\db\alt_u_div_7bf.tdf
Verilog_MyTest\db\alt_u_div_84f.tdf
Verilog_MyTest\db\alt_u_div_8af.tdf
Verilog_MyTest\db\alt_u_div_8bf.tdf
Verilog_MyTest\db\alt_u_div_9af.tdf
Verilog_MyTest\db\alt_u_div_9bf.tdf
Verilog_MyTest\db\alt_u_div_a7f.tdf
Verilog_MyTest\db\alt_u_div_aaf.tdf
Verilog_MyTest\db\alt_u_div_abf.tdf
Verilog_MyTest\db\alt_u_div_b7f.tdf
Verilog_MyTest\db\alt_u_div_baf.tdf
Verilog_MyTest\db\alt_u_div_bbf.tdf
Verilog_MyTest\db\alt_u_div_c7f.tdf
Verilog_MyTest\db\alt_u_div_caf.tdf
Verilog_MyTest\db\alt_u_div_cbf.tdf
Verilog_MyTest\db\alt_u_div_d7f.tdf
Verilog_MyTest\db\alt_u_div_daf.tdf
Verilog_MyTest\db\alt_u_div_dbf.tdf
Verilog_MyTest\db\alt_u_div_e7f.tdf
Verilog_MyTest\db\alt_u_div_eaf.tdf
Verilog_MyTest\db\alt_u_div_ebf.tdf
Verilog_MyTest\db\alt_u_div_f7f.tdf
Verilog_MyTest\db\alt_u_div_faf.tdf
Verilog_MyTest\db\alt_u_div_fbf.tdf
Verilog_MyTest\db\alt_u_div_g7f.tdf
Verilog_MyTest\db\alt_u_div_gaf.tdf
Verilog_MyTest\db\alt_u_div_gbf.tdf
Verilog_MyTest\db\alt_u_div_h7f.tdf
Verilog_MyTest\db\alt_u_div_haf.tdf
Verilog_MyTest\db\alt_u_div_hbf.tdf
Verilog_MyTest\db\alt_u_div_i7f.tdf
Verilog_MyTest\db\alt_u_div_iaf.tdf
Verilog_MyTest\db\alt_u_div_j7f.tdf
Verilog_MyTest\db\alt_u_div_jaf.tdf
Verilog_MyTest\db\alt_u_div_k7f.tdf
Verilog_MyTest\db\alt_u_div_kaf.tdf
Verilog_MyTest\db\alt_u_div_l7f.tdf
Verilog_MyTest\db\alt_u_div_laf.tdf
Verilog_MyTest\db\alt_u_div_m7f.tdf
Verilog_MyTest\db\alt_u_div_maf.tdf
Verilog_MyTest\db\alt_u_div_n7f.tdf
Verilog_MyTest\db\alt_u_div_naf.tdf
Verilog_MyTest\db\alt_u_div_o7f.tdf
Verilog_MyTest\db\alt_u_div_oaf.tdf
Verilog_MyTest\db\alt_u_div_paf.tdf