文件名称:zy1

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  • 硬件设计
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  • 2017-05-25
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  • 272kb
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  • 牛**
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基于quartusII利用VHDL语言实现逻辑与门的仿真并分析延时的影响-Based on quartusII using VHDL language to achieve logic and gate simulation and analysis of the impact of delay
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zy1\and_gate.asm.rpt

...\and_gate.bsf

...\and_gate.done

...\and_gate.fit.rpt

...\and_gate.fit.smsg

...\and_gate.fit.summary

...\and_gate.flow.rpt

...\and_gate.map.rpt

...\and_gate.map.summary

...\and_gate.pin

...\and_gate.pof

...\and_gate.qpf

...\and_gate.qsf

...\and_gate.qws

...\and_gate.sim.rpt

...\and_gate.sof

...\and_gate.tan.rpt

...\and_gate.tan.summary

...\and_gate.vhd

...\and_gate.vhd.bak

...\and_gate.vwf

...\db\and_gate.asm.qmsg

...\..\and_gate.asm.rdb

...\..\and_gate.asm_labs.ddb

...\..\and_gate.cbx.xml

...\..\and_gate.cmp.bpm

...\..\and_gate.cmp.cdb

...\..\and_gate.cmp.ecobp

...\..\and_gate.cmp.hdb

...\..\and_gate.cmp.kpt

...\..\and_gate.cmp.logdb

...\..\and_gate.cmp.rdb

...\..\and_gate.cmp.tdb

...\..\and_gate.cmp0.ddb

...\..\and_gate.cmp_merge.kpt

...\..\and_gate.db_info

...\..\and_gate.eco.cdb

...\..\and_gate.eds_overflow

...\..\and_gate.fit.qmsg

...\..\and_gate.hier_info

...\..\and_gate.hif

...\..\and_gate.lpc.html

...\..\and_gate.lpc.rdb

...\..\and_gate.lpc.txt

...\..\and_gate.map.bpm

...\..\and_gate.map.cdb

...\..\and_gate.map.ecobp

...\..\and_gate.map.hdb

...\..\and_gate.map.kpt

...\..\and_gate.map.logdb

...\..\and_gate.map.qmsg

...\..\and_gate.map_bb.cdb

...\..\and_gate.map_bb.hdb

...\..\and_gate.map_bb.logdb

...\..\and_gate.pre_map.cdb

...\..\and_gate.pre_map.hdb

...\..\and_gate.rtlv.hdb

...\..\and_gate.rtlv_sg.cdb

...\..\and_gate.rtlv_sg_swap.cdb

...\..\and_gate.sgdiff.cdb

...\..\and_gate.sgdiff.hdb

...\..\and_gate.sim.cvwf

...\..\and_gate.sim.hdb

...\..\and_gate.sim.qmsg

...\..\and_gate.sim.rdb

...\..\and_gate.sld_design_entry.sci

...\..\and_gate.sld_design_entry_dsc.sci

...\..\and_gate.smart_action.txt

...\..\and_gate.syn_hier_info

...\..\and_gate.tan.qmsg

...\..\and_gate.tis_db_list.ddb

...\..\logic_util_heursitic.dat

...\..\prev_cmp_and_gate.asm.qmsg

...\..\prev_cmp_and_gate.fit.qmsg

...\..\prev_cmp_and_gate.map.qmsg

...\..\prev_cmp_and_gate.qmsg

...\..\prev_cmp_and_gate.sim.qmsg

...\..\prev_cmp_and_gate.tan.qmsg

...\..\wed.wsf

...\incremental_db\compiled_partitions\and_gate.root_partition.cmp.cdb

...\..............\...................\and_gate.root_partition.cmp.dfp

...\..............\...................\and_gate.root_partition.cmp.hdb

...\..............\...................\and_gate.root_partition.cmp.kpt

...\..............\...................\and_gate.root_partition.cmp.logdb

...\..............\...................\and_gate.root_partition.cmp.rcfdb

...\..............\...................\and_gate.root_partition.cmp.re.rcfdb

...\..............\...................\and_gate.root_partition.map.cdb

...\..............\...................\and_gate.root_partition.map.dpi

...\..............\...................\and_gate.root_partition.map.hdb

...\..............\...................\and_gate.root_partition.map.kpt

...\..............\README

...\..............\compiled_partitions

...\db

...\incremental_db

zy1

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