文件名称:[verilog]dcfifo_256x32
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Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
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[verilog]dcfifo_256x32.v