文件名称:11_sdram_test
- 所属分类：
- 其他小程序
- 资源属性：
- [PDF]
- 上传时间：
- 2017-03-09
- 文件大小：
- 2.66mb
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- 0次
- 提 供 者：
- Wen Ju******
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module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
-module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
-module sdram_test(
input clk_50m,
input reset_n,
//sdram control
output S_CLK, //sdram clock
output S_CKE, //sdram clock enable
output S_NCS, //sdram chip select
output S_NWE, //sdram write enable
output S_NCAS, //sdram column address strobe
output S_NRAS, //sdram row address strobe
output [1:0] S_DQM, //sdram data enable
output [1:0] S_BA, //sdram bank address
output [12:0] S_A, //sdram address
inout [15:0] S_DB //sdram data
)
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下载文件列表
11_sdram_test\sdram_test\audio_test_summary.html
.............\..........\chipscope_icon.ngc
.............\..........\chipscope_icon.v
.............\..........\chipscope_ila.ngc
.............\..........\chipscope_ila.v
.............\..........\ipcore_dir\coregen.cgp
.............\..........\..........\coregen.log
.............\..........\..........\create_rdfifo.tcl
.............\..........\..........\create_rd_fif.tcl
.............\..........\..........\create_sdram_pll.tcl
.............\..........\..........\create_wrfifo.tcl
.............\..........\..........\edit_rdfifo.tcl
.............\..........\..........\edit_sdram_pll.tcl
.............\..........\..........\rdfifo\doc\fifo_generator_v9_3_readme.txt
.............\..........\..........\......\...\fifo_generator_v9_3_vinfo.html
.............\..........\..........\......\...\pg057-fifo-generator.pdf
.............\..........\..........\......\example_design\rdfifo_exdes.ucf
.............\..........\..........\......\..............\rdfifo_exdes.vhd
.............\..........\..........\......\fifo_generator_v9_3_readme.txt
.............\..........\..........\......\implement\implement.bat
.............\..........\..........\......\.........\implement.sh
.............\..........\..........\......\.........\implement_synplify.bat
.............\..........\..........\......\.........\implement_synplify.sh
.............\..........\..........\......\.........\planAhead_ise.bat
.............\..........\..........\......\.........\planAhead_ise.sh
.............\..........\..........\......\.........\planAhead_ise.tcl
.............\..........\..........\......\.........\xst.prj
.............\..........\..........\......\.........\xst.scr
.............\..........\..........\......\simulation\functional\simulate_isim.bat
.............\..........\..........\......\..........\..........\simulate_isim.sh
.............\..........\..........\......\..........\..........\simulate_mti.bat
.............\..........\..........\......\..........\..........\simulate_mti.do
.............\..........\..........\......\..........\..........\simulate_mti.sh
.............\..........\..........\......\..........\..........\simulate_ncsim.bat
.............\..........\..........\......\..........\..........\simulate_vcs.bat
.............\..........\..........\......\..........\..........\ucli_commands.key
.............\..........\..........\......\..........\..........\vcs_session.tcl
.............\..........\..........\......\..........\..........\wave_isim.tcl
.............\..........\..........\......\..........\..........\wave_mti.do
.............\..........\..........\......\..........\..........\wave_ncsim.sv
.............\..........\..........\......\..........\rdfifo_dgen.vhd
.............\..........\..........\......\..........\rdfifo_dverif.vhd
.............\..........\..........\......\..........\rdfifo_pctrl.vhd
.............\..........\..........\......\..........\rdfifo_pkg.vhd
.............\..........\..........\......\..........\rdfifo_rng.vhd
.............\..........\..........\......\..........\rdfifo_synth.vhd
.............\..........\..........\......\..........\rdfifo_tb.vhd
.............\..........\..........\......\..........\timing\simulate_isim.bat
.............\..........\..........\......\..........\......\simulate_isim.sh
.............\..........\..........\......\..........\......\simulate_mti.bat
.............\..........\..........\......\..........\......\simulate_mti.do
.............\..........\..........\......\..........\......\simulate_mti.sh
.............\..........\..........\......\..........\......\simulate_ncsim.bat
.............\..........\..........\......\..........\......\simulate_vcs.bat
.............\..........\..........\......\..........\......\ucli_commands.key
.............\..........\..........\......\..........\......\vcs_session.tcl
.............\..........\..........\......\..........\......\wave_isim.tcl
.............\..........\..........\......\..........\......\wave_mti.do
.............\..........\..........\......\..........\......\wave_