文件名称:digital-clock
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vhdl文件，实现数字钟，以及其顶层设计图-This package contains the VHDL file, can realize the digital clock, contains the top-level design
(系统自动生成,下载前可以参看下载内容)
下载文件列表
数字钟
......\Block.bdf
......\COUNT24.vwf
......\COUNT60.vwf
......\EDCL7S.bsf
......\EDCL7S.vhd
......\EDCL7S.vhd.bak
......\TIME.vwf
......\TIMEH.vwf
......\db
......\..\logic_util_heursitic.dat
......\..\main60.cbx.xml
......\..\main60.cmp.rdb
......\..\main60.cmp_merge.kpt
......\..\main60.db_info
......\..\main60.eco.cdb
......\..\main60.eds_overflow
......\..\main60.fnsim.cdb
......\..\main60.fnsim.hdb
......\..\main60.fnsim.qmsg
......\..\main60.hier_info
......\..\main60.hif
......\..\main60.lpc.html
......\..\main60.lpc.rdb
......\..\main60.lpc.txt
......\..\main60.map.bpm
......\..\main60.map.cdb
......\..\main60.map.ecobp
......\..\main60.map.hdb
......\..\main60.map.kpt
......\..\main60.map.logdb
......\..\main60.map.qmsg
......\..\main60.map_bb.cdb
......\..\main60.map_bb.hdb
......\..\main60.map_bb.logdb
......\..\main60.pre_map.cdb
......\..\main60.pre_map.hdb
......\..\main60.rtlv.hdb
......\..\main60.rtlv_sg.cdb
......\..\main60.rtlv_sg_swap.cdb
......\..\main60.sgdiff.cdb
......\..\main60.sgdiff.hdb
......\..\main60.sim.cvwf
......\..\main60.sim.hdb
......\..\main60.sim.qmsg
......\..\main60.sim.rdb
......\..\main60.simfam
......\..\main60.sld_design_entry.sci
......\..\main60.sld_design_entry_dsc.sci
......\..\main60.smart_action.txt
......\..\main60.syn_hier_info
......\..\main60.tis_db_list.ddb
......\..\mux_src.tdf
......\..\prev_cmp_main60.map.qmsg
......\..\prev_cmp_main60.sim.qmsg
......\..\prev_cmp_simple.qmsg
......\..\wed.wsf
......\incremental_db
......\..............\README
......\..............\compiled_partitions
......\..............\...................\main60.root_partition.map.cdb
......\..............\...................\main60.root_partition.map.dpi
......\..............\...................\main60.root_partition.map.hdb
......\..............\...................\main60.root_partition.map.kpt
......\main24.bsf
......\main24.vhd
......\main60.bsf
......\main60.done
......\main60.flow.rpt
......\main60.map.rpt
......\main60.map.summary
......\main60.qsf
......\main60.sim.rpt
......\main60.vhd
......\main60.vhd.bak
......\reg_16.vhd
......\simple.qpf
......\simple.qws