文件名称:145103015
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2016-11-26
- 文件大小：
- 1019kb
- 下载次数：
- 0次
- 提 供 者：
- abdel******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog source code for using keypad module with zybo fpga board to take input and show output to onboard leds and led module connected to GPIO
(系统自动生成,下载前可以参看下载内容)
下载文件列表
145103015\145103015.cache\wt\java_command_handlers.wdf
.........\...............\..\project.wpc
.........\...............\..\synthesis.wdf
.........\...............\..\synthesis_details.wdf
.........\...............\..\webtalk_pa.xml
.........\..........hw\145103015.lpr
.........\............\hw_1\hw.xml
.........\..........ip_user_files\ip\clk_core\clk_core.veo
.........\.......................\..\........\clk_core_stub.v
.........\.......................\..\........\clk_core_stub.vhdl
.........\.......................\..static\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh
.........\.......................\........\..............\mmcm_pll_drp_func_7s_pll.vh
.........\.......................\........\..............\mmcm_pll_drp_func_us_mmcm.vh
.........\.......................\........\..............\mmcm_pll_drp_func_us_pll.vh
.........\.......................\README.txt
.........\.......................\sim_scripts\clk_core\activehdl\clk_core.sh
.........\.......................\...........\........\.........\clk_core.udo
.........\.......................\...........\........\.........\compile.do
.........\.......................\...........\........\.........\file_info.txt
.........\.......................\...........\........\.........\glbl.v
.........\.......................\...........\........\.........\README.txt
.........\.......................\...........\........\.........\simulate.do
.........\.......................\...........\........\.........\wave.do
.........\.......................\...........\........\ies\clk_core.sh
.........\.......................\...........\........\...\file_info.txt
.........\.......................\...........\........\...\glbl.v
.........\.......................\...........\........\...\README.txt
.........\.......................\...........\........\...\run.f
.........\.......................\...........\........\modelsim\clk_core.sh
.........\.......................\...........\........\........\clk_core.udo
.........\.......................\...........\........\........\compile.do
.........\.......................\...........\........\........\file_info.txt
.........\.......................\...........\........\........\glbl.v
.........\.......................\...........\........\........\README.txt
.........\.......................\...........\........\........\simulate.do
.........\.......................\...........\........\........\wave.do
.........\.......................\...........\........\questa\clk_core.sh
.........\.......................\...........\........\......\clk_core.udo
.........\.......................\...........\........\......\compile.do
.........\.......................\...........\........\......\elaborate.do
.........\.......................\...........\........\......\file_info.txt
.........\.......................\...........\........\......\glbl.v
.........\.......................\...........\........\......\README.txt
.........\.......................\...........\........\......\simulate.do
.........\.......................\...........\........\......\wave.do
.........\.......................\...........\........\README.txt
.........\.......................\...........\........\riviera\clk_core.sh
.........\.......................\...........\........\.......\clk_core.udo
.........\.......................\...........\........\.......\compile.do
.........\.......................\...........\........\.......\file_info.txt
.........\.......................\...........\........\.......\glbl.v
.........\.......................\...........\........\.......\README.txt
.........\.......................\...........\........\.......\simulate.do
.........\.......................\...........\........\.......\wave.do
.........\.......................\...........\........\vcs\clk_core.sh
.........\.......................\...........\........\...\file_info.txt
.........\.......................\...........\........\...\glbl.v
.........\.......................\...........\........\...\README.txt
.........\.......................\...........\........\...\