文件名称:TFT_LCD

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  • [PDF]
  • 上传时间:
  • 2016-09-25
  • 文件大小:
  • 2.75mb
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  • 0次
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  • cha****
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产生逻辑画面的R/G/B/黑/白等画面的完整verilog源码,通过修改宏定义方便修改成支持各种尺寸的LCD驱动,本源码为RGB格式输出接口-Complete verilog source code generation logic screen R/G/B/black/white screen, etc., by modifying the macro definition modified to support a variety of convenient size LCD driver, the source for the RGB format and output interfaces
(系统自动生成,下载前可以参看下载内容)

下载文件列表





TFT_LCD\four_block_horizontal_gradient.v

.......\fuse.log

.......\fuse.xmsgs

.......\fuseRelaunch.cmd

.......\horizontal_gradient.v

.......\image_controller.v

.......\image_struct.v

.......\.pcore_dir\coregen.cgp

.......\..........\create_DCM_CLK.tcl

.......\..........\create_fifo_256_24.tcl

.......\..........\create_fifo_256_24bit.tcl

.......\..........\DCM_CLK\clk_wiz_v3_6_readme.txt

.......\..........\.......\doc\clk_wiz_v3_6_readme.txt

.......\..........\.......\...\clk_wiz_v3_6_vinfo.html

.......\..........\.......\...\pg065_clk_wiz.pdf

.......\..........\.......\example_design\DCM_CLK_exdes.ucf

.......\..........\.......\..............\DCM_CLK_exdes.v

.......\..........\.......\..............\DCM_CLK_exdes.xdc

.......\..........\.......\implement\implement.bat

.......\..........\.......\.........\implement.sh

.......\..........\.......\.........\planAhead_ise.bat

.......\..........\.......\.........\planAhead_ise.sh

.......\..........\.......\.........\planAhead_ise.tcl

.......\..........\.......\.........\planAhead_rdn.bat

.......\..........\.......\.........\planAhead_rdn.sh

.......\..........\.......\.........\planAhead_rdn.tcl

.......\..........\.......\.........\xst.prj

.......\..........\.......\.........\xst.scr

.......\..........\.......\simulation\DCM_CLK_tb.v

.......\..........\.......\..........\functional\simcmds.tcl

.......\..........\.......\..........\..........\simulate_isim.bat

.......\..........\.......\..........\..........\simulate_isim.sh

.......\..........\.......\..........\..........\simulate_mti.bat

.......\..........\.......\..........\..........\simulate_mti.do

.......\..........\.......\..........\..........\simulate_mti.sh

.......\..........\.......\..........\..........\simulate_ncsim.sh

.......\..........\.......\..........\..........\simulate_vcs.sh

.......\..........\.......\..........\..........\ucli_commands.key

.......\..........\.......\..........\..........\vcs_session.tcl

.......\..........\.......\..........\..........\wave.do

.......\..........\.......\..........\..........\wave.sv

.......\..........\.......\..........\timing\DCM_CLK_tb.v

.......\..........\.......\..........\......\sdf_cmd_file

.......\..........\.......\..........\......\simcmds.tcl

.......\..........\.......\..........\......\simulate_isim.sh

.......\..........\.......\..........\......\simulate_mti.bat

.......\..........\.......\..........\......\simulate_mti.do

.......\..........\.......\..........\......\simulate_mti.sh

.......\..........\.......\..........\......\simulate_ncsim.sh

.......\..........\.......\..........\......\simulate_vcs.sh

.......\..........\.......\..........\......\ucli_commands.key

.......\..........\.......\..........\......\vcs_session.tcl

.......\..........\.......\..........\......\wave.do

.......\..........\DCM_CLK.asy

.......\..........\DCM_CLK.gise

.......\..........\DCM_CLK.sym

.......\..........\DCM_CLK.ucf

.......\..........\DCM_CLK.v

.......\..........\DCM_CLK.veo

.......\..........\DCM_CLK.xco

.......\..........\DCM_CLK.xdc

.......\..........\DCM_CLK.xise

.......\..........\DCM_CLK_exdes.ncf

.......\..........\DCM_CLK_flist.txt

.......\..........\DCM_CLK_xmdf.tcl

.......\..........\edit_DCM_CLK.tcl

.......\..........\fifo_256_24bit\doc\fifo_generator_v9_2_readme.txt

.......\..........\..............\...\fifo_generator_v9_2_vinfo.html

.......\..........\..............\...\pg057-fifo-generator.pdf

.......\..........\..............\example_design\fifo_256_24bit_exdes.ucf

.......\..........\..............\..............\fifo_256_24bit_exdes.vhd

.......\..........\..............\..............\fifo_256_24bit_exdes.xdc

.......\..........\..............\fifo_generator_v9_2_readme.txt

.......\..........\..............\implement\implement.bat

.......\..........\..............\.........\implement.sh

.......\..........\..............\.........\implement_synplify.bat

.......\..........\..............\.........\implement_synplify.sh

.......\..........\..............\.........\planAhead_ise.bat

.......\..........\..............\.........\planAhead_ise.sh

.......\..........\.....

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