文件名称:UART-master
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UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART-master
...........\LICENSE
...........\README.md
...........\doc
...........\...\UART_IP_BRIF.pdf
...........\rtl
...........\...\UART.v
...........\...\uart_rx.v
...........\...\uart_tx.v
...........\systemC
...........\.......\link_sc.h
...........\testbench
...........\.........\module_tb.v
...........\vpi
...........\...\env_uart.cpp
...........\...\global_init.h
...........\...\reset_uart.h
...........\...\run_sim.h
...........\work
...........\....\UART_TEST_SUIT.glade
...........\....\run.sh
...........\....\sc_uart.so