文件名称:ahb_verilog_design
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代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
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下载文件列表
ahb_verilog_design\Simulation_files_SilosIII\ahbarb.v
..................\.........................\ahbdec.v
..................\.........................\ahbmst.v
..................\.........................\ahbslv.v
..................\.........................\ahb_def.v
..................\.........................\ahb_master.v
..................\.........................\ahb_slave.v
..................\.........................\ahb_stimuli.v
..................\.........................\appreq_sm.v
..................\.........................\app_codec.v
..................\.........................\busreq_sm.v
..................\.........................\demo_amba_for_tb.cfv
..................\.........................\demo_amba_for_tb.log
..................\.........................\demo_amba_for_tb.sim
..................\.........................\demo_amba_for_tb.spj
..................\.........................\demo_amba_for_tb.v
..................\.........................\fifo128x32.v
..................\.........................\macros.v
..................\.........................\r128a32_25um.v
..................\.........................\ram128x18_25um.v
..................\.........................\readme.txt
..................\.........................\save.hist
..................\.........................\testbench.v
..................\.........................\xor32x2.v
..................\.ynthesis_and_SpDE_files\ahb_master.v
..................\........................\ahb_slave.v
..................\........................\appreq_sm.v
..................\........................\app_codec.v
..................\........................\busreq_sm.v
..................\........................\demo_amba.atr
..................\........................\demo_amba.chp
..................\........................\demo_amba.plg
..................\........................\demo_amba.prd
..................\........................\demo_amba.prj
..................\........................\demo_amba.qdf
..................\........................\demo_amba.rpt
..................\........................\demo_amba.sc
..................\........................\demo_amba.sdf
..................\........................\demo_amba.spd
..................\........................\demo_amba.srm
..................\........................\demo_amba.srr
..................\........................\demo_amba.srs
..................\........................\demo_amba.tlg
..................\........................\demo_amba.v
..................\........................\demo_amba.vh
..................\........................\demo_amba.vq
..................\........................\fifo128x32.v
..................\........................\macros.v
..................\........................\qmipsesp.v
..................\........................\r128a32_25um.v
..................\........................\ram128x18_25um.v
..................\........................\spde.log
..................\........................\stdout.log
..................\........................\traplog.tlg
..................\........................\xor32x2.v
..................\Simulation_files_SilosIII
..................\Synthesis_and_SpDE_files
ahb_verilog_design