文件名称:LBG64_double_CLK
介绍说明--下载内容均来自于网络,请自行研究使用
数据压缩算法的硬件实现ASIC&FPGA(矢量量化算法)-Data compression algorithm implemented in hardware ASIC & FPGA (vector quantization algorithm)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LBG64_double_CLK
................\LBG.v
................\LBG.v.bak
................\LBG_64.cr.mti
................\LBG_64.mpf
................\LBG_tb.v
................\LBG_tb.v.bak
................\cal_disteu.v
................\cal_disteu.v.bak
................\clk_div.v
................\codebook_div.v
................\codebook_div.v.bak
................\codebook_init.v
................\codebook_init.v.bak
................\codebook_top.v
................\codebook_top.v.bak
................\codebook_update.v
................\codebook_update.v.bak
................\divider.v
................\divider.v.bak
................\mult.v
................\mult0.v
................\mult0.v.bak
................\mult2.v
................\mult2.v.bak
................\test_data.dat
................\transcript
................\vector_g.v
................\vector_g.v.bak
................\vsim.wlf
................\weight.v
................\work
................\....\@l@b@g
................\....\......\_primary.dat
................\....\......\_primary.dbs
................\....\......\_primary.vhd
................\....\......\verilog.asm
................\....\......\verilog.rw
................\....\_info
................\....\_temp
................\....\.....\vlog0f4bq9
................\....\.....\vlog0qh00v
................\....\.....\vlog1zv4q8
................\....\.....\vlog29qyze
................\....\.....\vlog3eg90j
................\....\.....\vlog4ym9x6
................\....\.....\vlog5iv8h4
................\....\.....\vlog79dz4c
................\....\.....\vlog7iyf87
................\....\.....\vlog9d12nz
................\....\.....\vlogb5jt7r
................\....\.....\vlogcd5xxf
................\....\.....\vlogebe5j0
................\....\.....\vloggr1e5y
................\....\.....\vlogixg7rk
................\....\.....\vlogjnvj11
................\....\.....\vlognan7i0
................\....\.....\vlogsf4vje
................\....\.....\vlogsjf52n
................\....\.....\vlogt1e73f
................\....\.....\vlogx1z1v7
................\....\.....\vlogy5ifeq
................\....\.....\vlogz1rstm
................\....\.....\vlogz2hd43
................\....\.....\vlogzdk2ej
................\....\_vmake
................\....\cal_disteu
................\....\..........\_primary.dat
................\....\..........\_primary.dbs
................\....\..........\_primary.vhd
................\....\..........\verilog.asm
................\....\..........\verilog.rw
................\....\clk_div
................\....\.......\_primary.dat
................\....\.......\_primary.dbs
................\....\.......\_primary.vhd
................\....\.......\verilog.asm
................\....\.......\verilog.rw
................\....\codebook_div
................\....\............\_primary.dat
................\....\............\_primary.dbs
................\....\............\_primary.vhd
................\....\............\verilog.asm
................\....\............\verilog.rw
................\....\codebook_init
................\....\.............\_primary.dat
................\....\.............\_primary.dbs
................\....\.............\_primary.vhd
................\....\.............\verilog.asm
................\....\.............\verilog.rw
................\....\codebook_top
................\....\............\_primary.dat
................\....\............\_primary.dbs
................\....\............\_primary.vhd
................\....\............\verilog.asm
................\....\............\verilog.rw
................\....\codebook_update
................\....\...............\_primary.dat
................\....\...............\_primary.dbs
................\....\...............\_primary.vhd