文件名称:TLC5620
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TLC5620串行DA转换,verilogHDL语言-TLC5620 DA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
TLC5620\DAC电路.JPG
.......\prj\db\TLC5620_CTRL.db_info
.......\...\..\TLC5620_CTRL.ipinfo
.......\...\..\TLC5620_CTRL.sld_design_entry.sci
.......\...\ip\CtrlWordSource.qip
.......\...\..\CtrlWordSource.v
.......\...\..\CtrlWordSource_bb.v
.......\...\..\greybox_tmp\cbx_args.txt
.......\...\output_files\TLC5620_CTRL.asm.rpt
.......\...\............\TLC5620_CTRL.done
.......\...\............\TLC5620_CTRL.eda.rpt
.......\...\............\TLC5620_CTRL.fit.rpt
.......\...\............\TLC5620_CTRL.fit.smsg
.......\...\............\TLC5620_CTRL.fit.summary
.......\...\............\TLC5620_CTRL.flow.rpt
.......\...\............\TLC5620_CTRL.jdi
.......\...\............\TLC5620_CTRL.map.rpt
.......\...\............\TLC5620_CTRL.map.summary
.......\...\............\TLC5620_CTRL.pin
.......\...\............\TLC5620_CTRL.sof
.......\...\............\TLC5620_CTRL.sta.rpt
.......\...\............\TLC5620_CTRL.sta.summary
.......\...\TLC5620_CTRL.qpf
.......\...\TLC5620_CTRL.qsf
.......\...\TLC5620_CTRL.qws
.......\...\TLC5620_CTRL_assignment_defaults.qdf
.......\...\TLC5620_CTRL_nativelink_simulation.rpt
.......\rtl\TCL5620_TOP.v
.......\...\TCL5620_TOP.v.bak
.......\...\TLC5620_CTRL.v
.......\...\TLC5620_CTRL.v.bak
.......\...\TLC5620_CTRL_tb.v
.......\...\TLC5620_CTRL_tb.v.bak
.......\prj\ip\greybox_tmp
.......\...\db
.......\...\ip
.......\...\output_files
.......\prj
.......\rtl
TLC5620