文件名称:FPGA_SDRAM
介绍说明－－下载内容均来自于网络，请自行研究使用
UART作为RS232协议的控制接口得到了广泛的应用，将UART的功能集成在FPGA芯片中，可使整个系统更为灵活、紧凑，减小整个电路的体积，提高系统的可靠性和稳定性。提出了一种基于FPGA的UART的实现方法，具体描述了发送、接收等模块的设计，恰当使用了有限状态机，实现了FPGA片上UART的设计，给出了仿真结果。-fpga verilog uart sram
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA读写SDRAM的实例
...................\vga_system
...................\..........\.sopc_builder
...................\..........\.............\install.ptf
...................\..........\.............\install2.ptf
...................\..........\.............\preferences.xml
...................\..........\FreeDevDAV.tcl
...................\..........\altpll0.bsf
...................\..........\altpll0.ppf
...................\..........\altpll0.v
...................\..........\altpll0_bb.v
...................\..........\altpll0_wave0.jpg
...................\..........\altpll0_waveforms.html
...................\..........\burst_0.v
...................\..........\cpu.v
...................\..........\cpu_bht_ram.mif
...................\..........\cpu_dc_tag_ram.mif
...................\..........\cpu_ic_tag_ram.mif
...................\..........\cpu_jtag_debug_module.v
...................\..........\cpu_jtag_debug_module_wrapper.v
...................\..........\cpu_mult_cell.v
...................\..........\cpu_ociram_default_contents.mif
...................\..........\cpu_rf_ram_a.mif
...................\..........\cpu_rf_ram_b.mif
...................\..........\cpu_test_bench.v
...................\..........\db
...................\..........\..\a_dpfifo_8t21.tdf
...................\..........\..\a_fefifo_7cf.tdf
...................\..........\..\a_gray2bin_ldb.tdf
...................\..........\..\a_graycounter_fgc.tdf
...................\..........\..\a_graycounter_ggc.tdf
...................\..........\..\a_graycounter_p96.tdf
...................\..........\..\alt_synch_pipe_0e8.tdf
...................\..........\..\alt_synch_pipe_1e8.tdf
...................\..........\..\altsyncram_9tl1.tdf
...................\..........\..\altsyncram_abn1.tdf
...................\..........\..\altsyncram_b4e1.tdf
...................\..........\..\altsyncram_chp1.tdf
...................\..........\..\altsyncram_cub1.tdf
...................\..........\..\altsyncram_e502.tdf
...................\..........\..\altsyncram_ji01.tdf
...................\..........\..\altsyncram_k1l1.tdf
...................\..........\..\altsyncram_l6e1.tdf
...................\..........\..\altsyncram_lde1.tdf
...................\..........\..\altsyncram_m6e1.tdf
...................\..........\..\altsyncram_mge1.tdf
...................\..........\..\altsyncram_reb1.tdf
...................\..........\..\altsyncram_t072.tdf
...................\..........\..\altsyncram_uce1.tdf
...................\..........\..\altsyncram_veb1.tdf
...................\..........\..\cntr_fjb.tdf
...................\..........\..\cntr_rj7.tdf
...................\..........\..\dcfifo_min1.tdf
...................\..........\..\decode_aoi.tdf
...................\..........\..\ded_mult_2o81.tdf
...................\..........\..\dffpipe_93c.tdf
...................\..........\..\dffpipe_mcc.tdf
...................\..........\..\dffpipe_pe9.tdf
...................\..........\..\dffpipe_qe9.tdf
...................\..........\..\dffpipe_re9.tdf
...................\..........\..\dpram_5h21.tdf
...................\..........\..\mult_add_4cr2.tdf
...................\..........\..\mult_add_6cr2.tdf
...................\..........\..\mux_1u7.tdf
...................\..........\..\prev_cmp_vga_system.fit.qmsg
...................\..........\..\prev_cmp_vga_system.map.qmsg
...................\..........\..\prev_cmp_vga_system.qmsg
...................\..........\..\scfifo_5n21.tdf
...................\..........\..\vga_system.asm.qmsg
...................\..........\..\vga_system.asm_labs.ddb
...................\..........\..\vga_system.cbx.xml
...................\..........\..\vga_system.cmp.bpm
...................\..........\..\vga_system.cmp.cdb
...................\..........\..\vga_system.cmp.ecobp
...................\..........\..\vga_system.cmp.hdb
...................\..........\..\vga_system.cmp.logdb
...................\..........\..\vga_system.cmp.rdb
...................\..........\..\vga_system.cmp.tdb
...................\..........\..\vga_system.cmp0.ddb
...................\..........\..\vga_system