文件名称:VerilogExperiment_v2
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Experiment_v2\Experiment02\simulation\modelsim\msim_transcript
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.............\..........22\01-vir_key_module\simulation\modelsim\msim_transcript
.............\............\.2-env_debounce_module\simulation\modelsim\msim_transcript
.............\...........3\simulation\modelsim\msim_transcript
.............\...........1\simulation\modelsim\msim_transcript
.............\...........4\01-tx_module\tx_module\simulation\modelsim\msim_transcript
.............\............\.2-enr_rx_module\simulation\modelsim\msim_transcript
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.............\...........6\sync_module\simulation\modelsim\msim_transcript
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.............\..........23\ps2_module\incremental_db\README
.............\...........4\02-enr_rx_module\rx_module\incremental_db\README
.............\............\.1-tx_module\tx_module\incremental_db\README
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.............\...........1\incremental_db\README
.............\...........2\01-vir_key_module\incremental_db\README
.............\............\.2-env_debounce_module\incremental_db\README
.............\...........3\incremental_db\README
.............\...........4\02-enr_rx_module\incremental_db\README
.............\...........5\incremental_db\README
.............\...........6\sync_module\incremental_db\README
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.............\...........3\ps2_module\transcript
.............\...........6\sync_module\transcript
.............\...........4\02-enr_rx_module\rx_module\transcript
.............\............\.1-tx_module\tx_module\transcript
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