文件名称:fpga-fir
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使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog language
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下载文件列表
fpga\fpga\db\.cbx.xml
....\....\..\add_sub_2jh.tdf
....\....\..\add_sub_3jh.tdf
....\....\..\add_sub_4jh.tdf
....\....\..\add_sub_5jh.tdf
....\....\..\add_sub_6jh.tdf
....\....\..\add_sub_7jh.tdf
....\....\..\add_sub_8jh.tdf
....\....\..\add_sub_98h.tdf
....\....\..\add_sub_9jh.tdf
....\....\..\add_sub_ajh.tdf
....\....\..\add_sub_c8h.tdf
....\....\..\add_sub_d8h.tdf
....\....\..\add_sub_e8h.tdf
....\....\..\add_sub_f8h.tdf
....\....\..\altsyncram_iqa1.tdf
....\....\..\FIR_DESIGN.cbx.xml
....\....\..\FIR_DESIGN.cmp.rdb
....\....\..\FIR_DESIGN.cmp_merge.kpt
....\....\..\FIR_DESIGN.db_info
....\....\..\FIR_DESIGN.eco.cdb
....\....\..\FIR_DESIGN.hier_info
....\....\..\FIR_DESIGN.hif
....\....\..\FIR_DESIGN.map.bpm
....\....\..\FIR_DESIGN.map.cdb
....\....\..\FIR_DESIGN.map.ecobp
....\....\..\FIR_DESIGN.map.hdb
....\....\..\FIR_DESIGN.map.kpt
....\....\..\FIR_DESIGN.map.logdb
....\....\..\FIR_DESIGN.map.qmsg
....\....\..\FIR_DESIGN.map_bb.cdb
....\....\..\FIR_DESIGN.map_bb.hdb
....\....\..\FIR_DESIGN.map_bb.hdbx
....\....\..\FIR_DESIGN.map_bb.logdb
....\....\..\FIR_DESIGN.pre_map.cdb
....\....\..\FIR_DESIGN.pre_map.hdb
....\....\..\FIR_DESIGN.psp
....\....\..\FIR_DESIGN.rtlv.hdb
....\....\..\FIR_DESIGN.rtlv_sg.cdb
....\....\..\FIR_DESIGN.rtlv_sg_swap.cdb
....\....\..\FIR_DESIGN.sgdiff.cdb
....\....\..\FIR_DESIGN.sgdiff.hdb
....\....\..\FIR_DESIGN.sld_design_entry.sci
....\....\..\FIR_DESIGN.sld_design_entry_dsc.sci
....\....\..\FIR_DESIGN.syn_hier_info
....\....\..\FIR_DESIGN.tis_db_list.ddb
....\....\..\prev_cmp_FIR_DESIGN.map.qmsg
....\....\..\prev_cmp_FIR_DESIGN.qmsg
....\....\FIR_DESIGN.done
....\....\FIR_DESIGN.flow.rpt
....\....\FIR_DESIGN.map.rpt
....\....\FIR_DESIGN.map.summary
....\....\FIR_DESIGN.qpf
....\....\FIR_DESIGN.qsf
....\....\FIR_DESIGN.qws
....\....\FIR_DESIGN.v
....\....\FIR_DESIGN.v.bak
....\....\fir_flt_lp_b3.bsf
....\....\fir_flt_lp_b3.cmp
....\....\fir_flt_lp_b3.inc
....\....\fir_flt_lp_b3.v
....\....\incremental_db\compiled_partitions\FIR_DESIGN.root_partition.map.atm
....\....\..............\...................\FIR_DESIGN.root_partition.map.dpi
....\....\..............\...................\FIR_DESIGN.root_partition.map.hdbx
....\....\..............\...................\FIR_DESIGN.root_partition.map.kpt
....\....\..............\README
....\....\original_data_rom.bsf
....\....\original_data_rom.cmp
....\....\original_data_rom.inc
....\....\original_data_rom.qip
....\....\original_data_rom.tdf
....\....\original_data_rom_wave0.jpg
....\....\original_data_rom_waveforms.html
....\....\incremental_db\compiled_partitions
....\....\db
....\....\incremental_db
....\fpga
fpga