文件名称:sp6ex18

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2016-01-30
  • 文件大小:
  • 4.85mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • l**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于Verilog HDL的对片内RAM进行连续读写测试实例-Based on the on-chip RAM for continuous reading and writing test cases for Verilog HDL
(系统自动生成,下载前可以参看下载内容)

下载文件列表





sp6ex18\counter.lso

.......\counter.prj

.......\counter.stx

.......\counter.xst

.......\ipcore_dir\chipscope\chipscope_debug.cdc

.......\..........\coregen.cgp

.......\..........\coregen.log

.......\..........\create_pll_controller.tcl

.......\..........\edit_pll_controller.tcl

.......\..........\pll_controller\clk_wiz_v3_6_readme.txt

.......\..........\..............\doc\clk_wiz_v3_6_readme.txt

.......\..........\..............\...\clk_wiz_v3_6_vinfo.html

.......\..........\..............\...\pg065_clk_wiz.pdf

.......\..........\..............\example_design\pll_controller_exdes.ucf

.......\..........\..............\..............\pll_controller_exdes.v

.......\..........\..............\..............\pll_controller_exdes.xdc

.......\..........\..............\implement\implement.bat

.......\..........\..............\.........\implement.sh

.......\..........\..............\.........\planAhead_ise.bat

.......\..........\..............\.........\planAhead_ise.sh

.......\..........\..............\.........\planAhead_ise.tcl

.......\..........\..............\.........\planAhead_rdn.bat

.......\..........\..............\.........\planAhead_rdn.sh

.......\..........\..............\.........\planAhead_rdn.tcl

.......\..........\..............\.........\xst.prj

.......\..........\..............\.........\xst.scr

.......\..........\..............\simulation\functional\simcmds.tcl

.......\..........\..............\..........\..........\simulate_isim.bat

.......\..........\..............\..........\..........\simulate_isim.sh

.......\..........\..............\..........\..........\simulate_mti.bat

.......\..........\..............\..........\..........\simulate_mti.do

.......\..........\..............\..........\..........\simulate_mti.sh

.......\..........\..............\..........\..........\simulate_ncsim.sh

.......\..........\..............\..........\..........\simulate_vcs.sh

.......\..........\..............\..........\..........\ucli_commands.key

.......\..........\..............\..........\..........\vcs_session.tcl

.......\..........\..............\..........\..........\wave.do

.......\..........\..............\..........\..........\wave.sv

.......\..........\..............\..........\pll_controller_tb.v

.......\..........\..............\..........\timing\pll_controller_tb.v

.......\..........\..............\..........\......\sdf_cmd_file

.......\..........\..............\..........\......\simcmds.tcl

.......\..........\..............\..........\......\simulate_isim.sh

.......\..........\..............\..........\......\simulate_mti.bat

.......\..........\..............\..........\......\simulate_mti.do

.......\..........\..............\..........\......\simulate_mti.sh

.......\..........\..............\..........\......\simulate_ncsim.sh

.......\..........\..............\..........\......\simulate_vcs.sh

.......\..........\..............\..........\......\ucli_commands.key

.......\..........\..............\..........\......\vcs_session.tcl

.......\..........\..............\..........\......\wave.do

.......\..........\pll_controller.asy

.......\..........\pll_controller.gise

.......\..........\pll_controller.ncf

.......\..........\pll_controller.sym

.......\..........\pll_controller.ucf

.......\..........\pll_controller.v

.......\..........\pll_controller.veo

.......\..........\pll_controller.xco

.......\..........\pll_controller.xdc

.......\..........\pll_controller.xise

.......\..........\pll_controller_flist.txt

.......\..........\pll_controller_xmdf.tcl

.......\..........\ram_controller\coregen.cgp

.......\..........\..............\coregen.log

.......\..........\..............\create_ram_controller.tcl

.......\..........\..............\edit_ram_controller.tcl

.......\..........\..............\ram_controller\blk_mem_gen_v7_3_readme.txt

.......\..........\..............\..............\doc\blk_mem_gen_v7_3_vinfo.html

.......\..........\..............\..............\...\pg058-blk-mem-gen.pdf

.......\..........\..............\..............\example_design\ram_controller_exdes.ucf

.......\..........\..............\.....

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org