文件名称:pll_prj
介绍说明－－下载内容均来自于网络，请自行研究使用
PLL配置仿真实验
PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟），
然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频
率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较
稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟），
然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频
率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较
稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pll_prj
.......\db
.......\..\logic_util_heursitic.dat
.......\..\pll_prj.db_info
.......\..\pll_prj.sld_design_entry.sci
.......\..\prev_cmp_pll_prj.eda.qmsg
.......\..\prev_cmp_pll_prj.fit.qmsg
.......\..\prev_cmp_pll_prj.map.qmsg
.......\..\prev_cmp_pll_prj.qmsg
.......\incremental_db
.......\..............\README
.......\..............\compiled_partitions
.......\..............\...................\pll_prj.db_info
.......\..............\...................\pll_prj.root_partition.cmp.dfp
.......\..............\...................\pll_prj.root_partition.cmp.kpt
.......\..............\...................\pll_prj.root_partition.cmp.logdb
.......\..............\...................\pll_prj.root_partition.map.dpi
.......\..............\...................\pll_prj.root_partition.map.kpt
.......\..............\...................\pll_prj.root_partition.merge_hb.atm
.......\pll_ctrl.ppf
.......\pll_ctrl.qip
.......\pll_ctrl.v
.......\pll_ctrl_bb.v
.......\pll_ctrl_inst.v
.......\pll_prj.asm.rpt
.......\pll_prj.done
.......\pll_prj.dpf
.......\pll_prj.eda.rpt
.......\pll_prj.fit.rpt
.......\pll_prj.fit.summary
.......\pll_prj.flow.rpt
.......\pll_prj.map.rpt
.......\pll_prj.map.summary
.......\pll_prj.pin
.......\pll_prj.pof
.......\pll_prj.qpf
.......\pll_prj.qsf
.......\pll_prj.qws
.......\pll_prj.sof
.......\pll_prj.v
.......\pll_prj_assignment_defaults.qdf
.......\pll_prj_nativelink_simulation.rpt
.......\simulation
.......\..........\modelsim
.......\..........\........\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\pll_prj.vt
.......\..........\........\pll_prj_run_msim_rtl_verilog.do
.......\..........\........\rtl_work
.......\..........\........\........\_info
.......\..........\........\........\_temp
.......\..........\........\........\_vmake
.......\..........\........\........\pll_ctrl
.......\..........\........\........\........\_primary.dat
.......\..........\........\........\........\_primary.dbs
.......\..........\........\........\........\_primary.vhd
.......\..........\........\........\........\verilog.prw
.......\..........\........\........\........\verilog.psm
.......\..........\........\........\pll_prj
.......\..........\........\........\.......\_primary.dat
.......\..........\........\........\.......\_primary.dbs
.......\..........\........\........\.......\_primary.vhd
.......\..........\........\........\.......\verilog.prw
.......\..........\........\........\.......\verilog.psm
.......\..........\........\........\pll_prj_vlg_tst
.......\..........\........\........\...............\_primary.dat
.......\..........\........\........\...............\_primary.dbs
.......\..........\........\........\...............\_primary.vhd
.......\..........\........\........\...............\verilog.prw
.......\..........\........\........\...............\verilog.psm
.......\..........\........\vsim.wlf