文件名称:uart

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2016-01-18
  • 文件大小:
  • 270kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Prud*****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块,分为发送模块,接受模块和波特率产生模块。-This routine is verilog hardware descr iption language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generator module.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





uart\db\logic_util_heursitic.dat

....\..\my_uart_top.asm.qmsg

....\..\my_uart_top.asm.rdb

....\..\my_uart_top.asm_labs.ddb

....\..\my_uart_top.cbx.xml

....\..\my_uart_top.cmp.cdb

....\..\my_uart_top.cmp.hdb

....\..\my_uart_top.cmp.kpt

....\..\my_uart_top.cmp.logdb

....\..\my_uart_top.cmp.rdb

....\..\my_uart_top.cmp.tdb

....\..\my_uart_top.cmp0.ddb

....\..\my_uart_top.db_info

....\..\my_uart_top.eco.cdb

....\..\my_uart_top.fit.qmsg

....\..\my_uart_top.hier_info

....\..\my_uart_top.hif

....\..\my_uart_top.lpc.html

....\..\my_uart_top.lpc.rdb

....\..\my_uart_top.lpc.txt

....\..\my_uart_top.map.cdb

....\..\my_uart_top.map.hdb

....\..\my_uart_top.map.logdb

....\..\my_uart_top.map.qmsg

....\..\my_uart_top.pre_map.cdb

....\..\my_uart_top.pre_map.hdb

....\..\my_uart_top.rpp.qmsg

....\..\my_uart_top.rtlv.hdb

....\..\my_uart_top.rtlv_sg.cdb

....\..\my_uart_top.rtlv_sg_swap.cdb

....\..\my_uart_top.sgate.rvd

....\..\my_uart_top.sgate_sm.rvd

....\..\my_uart_top.sgdiff.cdb

....\..\my_uart_top.sgdiff.hdb

....\..\my_uart_top.sld_design_entry.sci

....\..\my_uart_top.sld_design_entry_dsc.sci

....\..\my_uart_top.smart_action.txt

....\..\my_uart_top.syn_hier_info

....\..\my_uart_top.tan.qmsg

....\..\my_uart_top.tis_db_list.ddb

....\..\my_uart_top.tmw_info

....\..\prev_cmp_my_uart_top.asm.qmsg

....\..\prev_cmp_my_uart_top.fit.qmsg

....\..\prev_cmp_my_uart_top.map.qmsg

....\..\prev_cmp_my_uart_top.qmsg

....\..\prev_cmp_my_uart_top.tan.qmsg

....\incremental_db\compiled_partitions\my_uart_top.root_partition.map.kpt

....\..............\README

....\my_uart_rx.v

....\my_uart_top.asm.rpt

....\my_uart_top.done

....\my_uart_top.dpf

....\my_uart_top.fit.rpt

....\my_uart_top.fit.smsg

....\my_uart_top.fit.summary

....\my_uart_top.flow.rpt

....\my_uart_top.map.rpt

....\my_uart_top.map.summary

....\my_uart_top.pin

....\my_uart_top.pof

....\my_uart_top.qpf

....\my_uart_top.qsf

....\my_uart_top.qsf.bak

....\my_uart_top.qws

....\my_uart_top.tan.rpt

....\my_uart_top.tan.summary

....\my_uart_top.v

....\my_uart_top_assignment_defaults.qdf

....\my_uart_tx.v

....\speed_select.v

....\incremental_db\compiled_partitions

....\db

....\incremental_db

uart

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