文件名称:FSM
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog编写的FPGA有限状态机一段式描述。-The FSM of FPGA based on Verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
20151125
........\db
........\..\logic_util_heursitic.dat
........\..\Meng.cbx.xml
........\..\Meng.cmp.rdb
........\..\Meng.cmp_merge.kpt
........\..\Meng.db_info
........\..\Meng.hier_info
........\..\Meng.hif
........\..\Meng.lpc.html
........\..\Meng.lpc.rdb
........\..\Meng.lpc.txt
........\..\Meng.map.bpm
........\..\Meng.map.cdb
........\..\Meng.map.hdb
........\..\Meng.map.kpt
........\..\Meng.map.logdb
........\..\Meng.map.qmsg
........\..\Meng.map_bb.cdb
........\..\Meng.map_bb.hdb
........\..\Meng.map_bb.logdb
........\..\Meng.pre_map.cdb
........\..\Meng.pre_map.hdb
........\..\Meng.rtlv.hdb
........\..\Meng.rtlv_sg.cdb
........\..\Meng.rtlv_sg_swap.cdb
........\..\Meng.sgdiff.cdb
........\..\Meng.sgdiff.hdb
........\..\Meng.sld_design_entry.sci
........\..\Meng.sld_design_entry_dsc.sci
........\..\Meng.smart_action.txt
........\..\Meng.smp_dump.txt
........\..\Meng.syn_hier_info
........\..\Meng.tis_db_list.ddb
........\..\prev_cmp_Meng.qmsg
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\Meng.db_info
........\..............\...................\Meng.root_partition.map.cdb
........\..............\...................\Meng.root_partition.map.dpi
........\..............\...................\Meng.root_partition.map.hbdb.cdb
........\..............\...................\Meng.root_partition.map.hbdb.hb_info
........\..............\...................\Meng.root_partition.map.hbdb.hdb
........\..............\...................\Meng.root_partition.map.hbdb.sig
........\..............\...................\Meng.root_partition.map.hdb
........\..............\...................\Meng.root_partition.map.kpt
........\..............\README
........\Meng.bdf
........\Meng.done
........\Meng.flow.rpt
........\Meng.map.rpt
........\Meng.map.smsg
........\Meng.map.summary
........\Meng.qpf
........\Meng.qsf
........\Meng_nativelink_simulation.rpt
........\simulation
........\..........\modelsim
........\..........\........\Meng_run_msim_rtl_verilog.do
........\..........\........\Meng_run_msim_rtl_verilog.do.bak
........\..........\........\msim_transcript
........\..........\........\rtl_work
........\..........\........\........\@_opt
........\..........\........\........\.....\vopt2vdjgt
........\..........\........\........\.....\vopt2y5rdq
........\..........\........\........\.....\vopt2zfhas
........\..........\........\........\.....\vopt64wrmq
........\..........\........\........\.....\vopt6qvmaq
........\..........\........\........\.....\vopta7hiaq
........\..........\........\........\.....\voptd2eajt
........\..........\........\........\.....\voptdj5enq
........\..........\........\........\.....\voptgzt98q
........\..........\........\........\.....\vopth3vbnq
........\..........\........\........\.....\vopthi36jt
........\..........\........\........\.....\voptkjg8nq
........\..........\........\........\.....\voptkrg55q
........\..........\........\........\.....\voptr122ir
........\..........\........\........\.....\voptr1dxjt
........\..........\........\........\.....\voptr365nq
........\..........\........\........\.....\voptvh2tjt
........\..........\........\........\.....\voptzarqgt
........\..........\........\........\.....\voptzvfvjq
........\..........\........\........\.....\_deps
........\..........\........\........\squen_1s
........\..........\........\........\........\_primary.dat
........\..........\........\........\........\_primary.dbs
........\..........\........\........\........\_primary.vhd
........\..........\........\........\squen_1s_tb
........\..........\........\........\...........\_primary.dat
........\..........\........\........\...........\_primary.dbs
........\..........\........\........\...........\_primary.vhd
........\..........\........\........\_info
........\..........\........\........\_temp
........\..........\........\........\_vmake
........\..........\........\verilog_libs
........\..........\........\............\altera_lnsim_ver
........\..........\........\............\................\altera_gen