文件名称:clk_generator
- 所属分类：
- VHDL编程
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2015-12-13
- 文件大小：
- 381kb
- 下载次数：
- 0次
- 提 供 者：
- duzen*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_generator\clk_generator.gise
.............\clk_generator.v
.............\clk_generator.xise
.............\clk_generator_summary.html
.............\fuse.log
.............\fuse.xmsgs
.............\fuseRelaunch.cmd
.............\iseconfig\clk_generator.projectmgr
.............\.........\clk_generator.xreport
.............\..im\isim_usage_statistics.html
.............\....\pn_info
.............\....\tb_clk_isim_beh.exe.sim\isimcrash.log
.............\....\.......................\ISimEngine-DesignHierarchy.dbg
.............\....\.......................\isimkernel.log
.............\....\.......................\libPortability.dll
.............\....\.......................\netId.dat
.............\....\.......................\tb_clk_isim_beh.exe
.............\....\.......................\.mp_save\_1
.............\....\.......................\work\m_00000000002925983510_1875869201.c
.............\....\.......................\....\m_00000000002925983510_1875869201.didat
.............\....\.......................\....\m_00000000002925983510_1875869201.nt64.obj
.............\....\.......................\....\m_00000000003307618390_3456128000.c
.............\....\.......................\....\m_00000000003307618390_3456128000.didat
.............\....\.......................\....\m_00000000003307618390_3456128000.nt64.obj
.............\....\.......................\....\m_00000000004134447467_2073120511.c
.............\....\.......................\....\m_00000000004134447467_2073120511.didat
.............\....\.......................\....\m_00000000004134447467_2073120511.nt64.obj
.............\....\.......................\....\tb_clk_isim_beh.exe_main.c
.............\....\.......................\....\tb_clk_isim_beh.exe_main.nt64.obj
.............\....\work\clk_generator.sdb
.............\....\....\glbl.sdb
.............\....\....\tb_clk.sdb
.............\isim.cmd
.............\isim.log
.............\tb_clk.v
.............\tb_clk_beh.prj
.............\tb_clk_generator.v
.............\tb_clk_isim_beh.exe
.............\tb_clk_isim_beh.wdb
.............\xilinxsim.ini
.............\_xmsgs\pn_parser.xmsgs
.............\isim\tb_clk_isim_beh.exe.sim\tmp_save
.............\....\.......................\work
.............\....\tb_clk_isim_beh.exe.sim
.............\....\work
.............\ipcore_dir
.............\iseconfig
.............\isim
.............\_xmsgs
clk_generator