文件名称:zhuangtaiji
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verilog一个有趣的状态机事例，简单易懂。适用于初学者。是一个小游戏的，sparten板子可用。
内含测试。-Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available.
Inclusion test.
内含测试。-Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available.
Inclusion test.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
One_step.pdf
one_step.v
One_step_ISE窗口.png
Three_step.pdf
three_step.v
Three_step_ISE窗口.png
Two_step.pdf
two_step.v
Two_step_ISE窗口.png