文件名称:demoss
- 所属分类：
- VHDL编程
- 资源属性：
- [HTML]
- 上传时间：
- 2015-10-26
- 文件大小：
- 20.1mb
- 下载次数：
- 0次
- 提 供 者：
- ruangu******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA的代码verilog语言编写，包括LED与按键验证，数据选择器，编码器，译码器半加器，全加器，适合初学者，已经在板子调试成功，板子是 睿智IV开发板。-FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been successful commissioning of the board, the board is wise IV development board.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
数字逻辑基础篇07：一位全加器\full_adder
............................\..........\db
............................\..........\..\full_adder.amm.cdb
............................\..........\..\full_adder.asm.qmsg
............................\..........\..\full_adder.asm.rdb
............................\..........\..\full_adder.asm_labs.ddb
............................\..........\..\full_adder.cbx.xml
............................\..........\..\full_adder.cmp.bpm
............................\..........\..\full_adder.cmp.cdb
............................\..........\..\full_adder.cmp.hdb
............................\..........\..\full_adder.cmp.kpt
............................\..........\..\full_adder.cmp.logdb
............................\..........\..\full_adder.cmp.rdb
............................\..........\..\full_adder.cmp_merge.kpt
............................\..........\..\full_adder.cmp2.ddb
............................\..........\..\full_adder.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
............................\..........\..\full_adder.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
............................\..........\..\full_adder.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
............................\..........\..\full_adder.db_info
............................\..........\..\full_adder.fit.qmsg
............................\..........\..\full_adder.hier_info
............................\..........\..\full_adder.hif
............................\..........\..\full_adder.idb.cdb
............................\..........\..\full_adder.lpc.html
............................\..........\..\full_adder.lpc.rdb
............................\..........\..\full_adder.lpc.txt
............................\..........\..\full_adder.map.bpm
............................\..........\..\full_adder.map.cdb
............................\..........\..\full_adder.map.hdb
............................\..........\..\full_adder.map.kpt
............................\..........\..\full_adder.map.logdb
............................\..........\..\full_adder.map.qmsg
............................\..........\..\full_adder.map_bb.cdb
............................\..........\..\full_adder.map_bb.hdb
............................\..........\..\full_adder.map_bb.logdb
............................\..........\..\full_adder.pre_map.cdb
............................\..........\..\full_adder.pre_map.hdb
............................\..........\..\full_adder.rtlv.hdb
............................\..........\..\full_adder.rtlv_sg.cdb
............................\..........\..\full_adder.rtlv_sg_swap.cdb
............................\..........\..\full_adder.sgdiff.cdb
............................\..........\..\full_adder.sgdiff.hdb
............................\..........\..\full_adder.sld_design_entry.sci
............................\..........\..\full_adder.sld_design_entry_dsc.sci
............................\..........\..\full_adder.smart_action.txt
............................\..........\..\full_adder.sta.qmsg
............................\..........\..\full_adder.sta.rdb
............................\..........\..\full_adder.sta_cmp.8_slow_1200mv_85c.tdb
............................\..........\..\full_adder.syn_hier_info
............................\..........\..\full_adder.tis_db_list.ddb
............................\..........\..\full_adder.tiscmp.fast_1200mv_0c.ddb
............................\..........\..\full_adder.tiscmp.fastest_slow_1200mv_0c.ddb
............................\..........\..\full_adder.tiscmp.fastest_slow_1200mv_85c.ddb
............................\..........\..\full_adder.tiscmp.slow_1200mv_0c.ddb
............................\..........\..\full_adder.tiscmp.slow_1200mv_85c.ddb
............................\..........\..\full_adder.tmw_info
............................\..........\..\logic_util_heursitic.dat
............................\..........\..\prev_cmp_full_adder.qmsg
............................\..........\full_adder.asm.rpt
............................\..........\full_adder.done
............................\.........