文件名称:c5
介绍说明－－下载内容均来自于网络，请自行研究使用
加法器、乘法器、除法器、DDS函数信号发生器等FPGA实现-Some signal generator build by FPGA！
(系统自动生成,下载前可以参看下载内容)
下载文件列表
5-1\adder16_2.v
..2\add_4.v
..3\adder.xco
...\adder1.v
..4\ade.v
..5\mul_addtree.v
..6\cmultip.v
...\rmulti.xco
..7\mult_8.v
..9\divider.v
..10\div16.xco
....\div16_1.v
...1\divf16.xco
....\divf16_1.v
...5\dds.v
....\rom_cos.coe
....\rom_cose.xco
....\rom_sin.coe
....\rom_sine.xco
...6\dds1.v
....\mydds.xco
...7\cordic.v
...8\sqrt.xco
....\sqrt1.v
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-9
5-10
5-11
5-15
5-16
5-17
5-18