文件名称:Verilog-HDL-Code-Examples
介绍说明－－下载内容均来自于网络，请自行研究使用
various verilog code ezamples for brginners.good point to start with.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Code_3\ask_2.v
......\ask_2_de.v
......\fsk_2.v
......\fsk_2_de.v
......\ppm.v
......\ppm_de.v
......\psk_2.v
......\psk_2_de.v
......\qpsk.v
......\qpsk_de.v
.....4\CONTROLLER.v
......\CSEEBLOCK.v
......\KESBLOCK.V
......\RSDECODER.v
......\RS_ENCODER.V
......\SCBLOCK.V
.....5\5.1\GENSQUE.v
......\...\GOLD_SQUE_GEN.v
......\..2\SPR_SPECTRUM_MOD.v
......\..3\CATCH_TOP.v
......\...\CATCH_TOP.v.bak
......\...\GATE_CONTROL.v
......\...\GATE_CONTROL.v.bak
......\...\GENSQUE.v
......\...\GENSQUE.v.bak
......\...\SERIAL_SOLVE.v
......\...\SERIAL_SOLVE.v.bak
......\...\SERIAL_TO_PARALLEL.v
......\...\SERIAL_TO_PARALLEL.v.bak
......\...\TESTBENCH.v
......\...\TESTBENCH.v.bak
.....6\BAUD_GENERATER.v
......\SERIAL_CONTROLLER.v
......\UART_RECEIVER.v
......\UART_TRANSMITTER.v
.....7\7.1\DESCRAMBLER.v
......\...\PARALLEL_SCRAMBLER.v
......\...\PARALLEL_SCRAM_TEST.v
......\...\PARALLER_DESCRAMBLER.v
......\...\SCRAMBLER.v
......\...\SCRAM_TEST.v
......\..2\CRC16.v
......\...\CRC_16_PARALLEL.v
......\..3\SDH_STM1.v
......\..4\DECODE_8B_10B.v
......\...\ENCODE_8B_10B.v
.....1\add_full.v
......\add_half.v
......\count16.v
......\decode3to8.v
......\fifo3.v
......\fre13.v
......\mult1from8.v
......\ram_4_4.v
......\rom_16_4.v
......\ser_to_parr.v
......\trigger_d.v
......\trigger_jk.v
......\trigger_rs.v
.....2\cic_filter_3__28_ho.v
......\cic_insert_3_2_8_ho.v
......\decimate_4.v
......\fir_lp_8.v
......\fir_parr_8.v
......\iir_cascade_2.v
......\iir_filter_8.v
......\insert_4.v
.....5\5.1
......\5.2
......\5.3
.....7\7.1
......\7.2
......\7.3
......\7.4
Code_3
Code_4
Code_5
Code_6
Code_7
Code_1
Code_2