文件名称:SDRAM_interface
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SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits.
1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode
2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode
2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
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SDRAM_interface.v