文件名称:NiosII_SPI_bus

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [MacOS] [WORD]
  • 上传时间:
  • 2015-06-28
  • 文件大小:
  • 2.82mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • le***
  • 相关连接:
  • 下载说明:
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采用altera公司EP3C系列芯片实现的基于Nios II的SPI总线设计,采用Verilog编码-Altera company EP3C using the Nios II series chip SPI bus-based design, using Verilog coding
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下载文件列表





24章 基于Nios II的SPI总线设计\~$篇第17章基于Nios II的SPI总线设计.doc

.............................\spipro\clock_0.v

.............................\......\clock_0.vhd

.............................\......\clock_1.v

.............................\......\clock_1.vhd

.............................\......\cpu.ocp

.............................\......\cpu.v

.............................\......\cpu.vhd

.............................\......\cpu_bht_ram.mif

.............................\......\cpu_dc_tag_ram.mif

.............................\......\cpu_ic_tag_ram.mif

.............................\......\cpu_jtag_debug_module.v

.............................\......\cpu_jtag_debug_module.vhd

.............................\......\cpu_jtag_debug_module_wrapper.v

.............................\......\cpu_jtag_debug_module_wrapper.vhd

.............................\......\cpu_mult_cell.v

.............................\......\cpu_mult_cell.vhd

.............................\......\cpu_ociram_default_contents.mif

.............................\......\cpu_rf_ram_a.mif

.............................\......\cpu_rf_ram_b.mif

.............................\......\cpu_test_bench.v

.............................\......\cpu_test_bench.vhd

.............................\......\CS.v

.............................\......\CS.vhd

.............................\......\epcs_controller.v

.............................\......\epcs_controller.vhd

.............................\......\epcs_controller_boot_rom.hex

.............................\......\jtag_uart.v

.............................\......\jtag_uart.vhd

.............................\......\niospll.bsf

.............................\......\niospll.cmp

.............................\......\niospll.ppf

.............................\......\niospll.v

.............................\......\niospll_bb.v

.............................\......\niospll_wave0.jpg

.............................\......\niospll_waveforms.html

.............................\......\onchip_mem.hex

.............................\......\onchip_mem.v

.............................\......\onchip_mem.vhd

.............................\......\pinset.tcl

.............................\......\pio_SDATA.vhd

.............................\......\SCLK.v

.............................\......\SCLK.vhd

.............................\......\SDATA.v

.............................\......\SDATA.vhd

.............................\......\sdram.v

.............................\......\sdram.vhd

.............................\......\sdram_test_component.v

.............................\......\sdram_test_component.vhd

.............................\......\sopc_builder_log.txt

.............................\......\SPINIOS.bsf

.............................\......\SPINIOS.ptf

.............................\......\SPINIOS.ptf.bak

.............................\......\SPINIOS.ptf.pre_generation_ptf

.............................\......\SPINIOS.qip

.............................\......\SPINIOS.sopc

.............................\......\SPINIOS.v

.............................\......\SPINIOS.vhd

.............................\......\SPINIOS_generation_script

.............................\......\SPINIOS_log.txt

.............................\......\SPINIOS_setup_quartus.tcl

.............................\......\spipll.bsf

.............................\......\spipll.cmp

.............................\......\spipll.ppf

.............................\......\spipll.vhd

.............................\......\spipll_wave0.jpg

.............................\......\spipll_waveforms.html

.............................\......\spipro.asm.rpt

.............................\......\spipro.bdf

.............................\......\spipro.done

.............................\......\spipro.fit.rpt

.............................\......\spipro.fit.smsg

.............................\......\spipro.fit.summary

.............................\......\spipro.flow.rpt

.............................\......\spipro.jdi

.............................\......\spipro.map.rpt

.............................\......\spipro.map.summary

...........................

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