文件名称:Caculator
介绍说明－－下载内容均来自于网络，请自行研究使用
基于Verilog语言编写的简易计算器，实现了加减法的运算，有模块和约束文件。-Verilog language based on simple calculator, to achieve the operation of addition and subtraction, there are modules and constraint files.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
计算器
......\ADD_CORE.v
......\CLK_DIV.v
......\CORE_CALCULATE.v
......\DEBOUNCE.v
......\KEY_SCAN.v
......\KEY_SCAN1.v
......\LED_ALU.v
......\LED_SCAN.v
......\LED_TRANS.v
......\SUB_CORE.v
......\TRAN_HEX_LED.v
......\main.ucf
......\main.v
......\tb.v
......\test_core.v
......\v4_dcm.v