文件名称:Asynchronous-FIFO-
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异步FIFO是一种先进先出电路，可以有效解决异步时钟之间的数据传递。通过分析异步FIFO设计中的难点，以降低电路中亚稳态出现的概率为主要目的，大大提高工作频率和资源利用率。-Asynchronous FIFO is an advanced circuit that can effectively solve the data transfer between asynchronous clock. Through the analysis of the difficulties in asynchronous FIFO design, the probability of the Central Asian steady state is the main purpose, greatly improving the working frequency and resource utilization..
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下载文件列表
异步FIFO设计\async_cmp.v
............\async_fifo.v
............\dp_ram.v
............\rptr_empty.v
............\wptr_full.v
异步FIFO设计