文件名称:NCO

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2015-05-13
  • 文件大小:
  • 5.56mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 孙**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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基于FPGA的DDS设计,通过外接DA转换器输出稳定的正弦波,方波和三角波,可单独产生时钟,不必借助硬件连接,包含寄存器程序,累加器程序和时钟发生电路等,以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help of the hardware connection, including the register program, accumulator program and a clock generation circuit, and a top design schematics
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下载文件列表





NCO

...\.Xil

...\....\PlanAhead-2968-PC-201209030931

...\....\..............................\ngc2edif

...\....\..............................\........\_xmsgs

...\....\..............................\........\......\ngc2edif.xmsgs

...\....\..............................\........\nco.edif

...\....\..............................\........\ngc2edif.log

...\....\..............................\........\rom.edif

...\.lso

...\KDATA.cmd_log

...\KDATA.prj

...\KDATA.spl

...\KDATA.stx

...\KDATA.sym

...\KDATA.vhd

...\KDATA.xst

...\KDATA_vhdl.prj

...\NCO.gise

...\NCO.xise

...\TEST_K.vhd

...\TEST_K_beh.prj

...\TEST_K_isim_beh.exe

...\TEST_K_isim_beh.wdb

...\TEST_K_stx_beh.prj

...\_ngo

...\....\netlist.lst

...\_xmsgs

...\......\bitgen.xmsgs

...\......\map.xmsgs

...\......\netgen.xmsgs

...\......\ngdbuild.xmsgs

...\......\par.xmsgs

...\......\pn_parser.xmsgs

...\......\trce.xmsgs

...\......\xst.xmsgs

...\crc_test.vhd

...\crc_test_beh.prj

...\crc_test_isim_beh.exe

...\crc_test_isim_beh.wdb

...\crc_test_stx_beh.prj

...\create_clk.cmd_log

...\create_clk.prj

...\create_clk.spl

...\create_clk.stx

...\create_clk.sym

...\create_clk.vhd

...\create_clk.xst

...\create_clk_vhdl.prj

...\fuse.log

...\fuse.xmsgs

...\fuseRelaunch.cmd

...\ipcore_dir

...\..........\_xmsgs

...\..........\......\cg.xmsgs

...\..........\......\pn_parser.xmsgs

...\..........\coregen.cgp

...\..........\coregen.log

...\..........\create_PP.tcl

...\..........\create_d.tcl

...\..........\create_dcm.tcl

...\..........\create_rom.tcl

...\..........\edit_rom.tcl

...\..........\rom

...\..........\...\blk_mem_gen_v7_3_readme.txt

...\..........\...\doc

...\..........\...\...\blk_mem_gen_v7_3_vinfo.html

...\..........\...\...\pg058-blk-mem-gen.pdf

...\..........\...\example_design

...\..........\...\..............\rom_exdes.ucf

...\..........\...\..............\rom_exdes.vhd

...\..........\...\..............\rom_exdes.xdc

...\..........\...\..............\rom_prod.vhd

...\..........\...\implement

...\..........\...\.........\implement.bat

...\..........\...\.........\implement.sh

...\..........\...\.........\planAhead_ise.bat

...\..........\...\.........\planAhead_ise.sh

...\..........\...\.........\planAhead_ise.tcl

...\..........\...\.........\xst.prj

...\..........\...\.........\xst.scr

...\..........\...\simulation

...\..........\...\..........\addr_gen.vhd

...\..........\...\..........\bmg_stim_gen.vhd

...\..........\...\..........\bmg_tb_pkg.vhd

...\..........\...\..........\functional

...\..........\...\..........\..........\simcmds.tcl

...\..........\...\..........\..........\simulate_isim.bat

...\..........\...\..........\..........\simulate_mti.bat

...\..........\...\..........\..........\simulate_mti.do

...\..........\...\..........\..........\simulate_mti.sh

...\..........\...\..........\..........\simulate_ncsim.sh

...\..........\...\..........\..........\simulate_vcs.sh

...\..........\...\..........\..........\ucli_commands.key

...\..........\...\..........\..........\vcs_session.tcl

...\..........\...\..........\..........\wave_mti.do

...\..........\...\..........\..........\wave_ncsim.sv

...\..........\...\..........\random.vhd

...\..........\...\..........\rom_synth.vhd

...\..........\...\..........\rom_tb.vhd

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