文件名称:cf_vhdl
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CF VHDL
The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
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下载文件列表
压缩包 : 95302899cf_vhdl.rar 列表 cf_plus.npl cf_plus.rpt cf_plus.ucf cf_plus.vcd cf_plus.vhd cf_plus_control.vhd cis.vhd dsp_interface.vhd initfile.dat readme.txt test_func.do test_post.do testbench.vhd timesim.vhd upcnt6.vhd wave_func.do wave_post.do attribute_memory.vhd cf_plus.cxt cf_plus.jed