文件名称:ex9_cof_M4K_test1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2015-04-17
  • 文件大小:
  • 3.87mb
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  • 0次
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  • 焦**
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FPGA器件中通常嵌入一些用户可配置的存储块,此代码是关于基M4K块的单RAM配置仿真实验。  -FPGA devices are usually embedded memory blocks some user-configurable, this code is based on a single M4K block RAM configuration simulation.
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ex9_cof_M4K_test1\db\altsyncram_oaa1.tdf

.................\..\logic_util_heursitic.dat

.................\..\mem_cof.db_info

.................\..\mem_cof.sld_design_entry.sci

.................\..\mem_cof_global_asgn_op.abo

.................\..\prev_cmp_mem_cof.asm.qmsg

.................\..\prev_cmp_mem_cof.eda.qmsg

.................\..\prev_cmp_mem_cof.fit.qmsg

.................\..\prev_cmp_mem_cof.map.qmsg

.................\..\prev_cmp_mem_cof.qmsg

.................\..\prev_cmp_mem_cof.tan.qmsg

.................\incremental_db\compiled_partitions\mem_cof.db_info

.................\..............\...................\mem_cof.root_partition.cmp.atm

.................\..............\...................\mem_cof.root_partition.cmp.dfp

.................\..............\...................\mem_cof.root_partition.cmp.hdbx

.................\..............\...................\mem_cof.root_partition.cmp.kpt

.................\..............\...................\mem_cof.root_partition.cmp.logdb

.................\..............\...................\mem_cof.root_partition.cmp.rcf

.................\..............\...................\mem_cof.root_partition.map.atm

.................\..............\...................\mem_cof.root_partition.map.dpi

.................\..............\...................\mem_cof.root_partition.map.hdbx

.................\..............\...................\mem_cof.root_partition.map.kpt

.................\..............\README

.................\mem_cof.asm.rpt

.................\mem_cof.done

.................\mem_cof.eda.rpt

.................\mem_cof.fit.rpt

.................\mem_cof.fit.smsg

.................\mem_cof.fit.summary

.................\mem_cof.flow.rpt

.................\mem_cof.map.rpt

.................\mem_cof.map.summary

.................\mem_cof.pin

.................\mem_cof.pof

.................\mem_cof.qpf

.................\mem_cof.qsf

.................\mem_cof.qws

.................\mem_cof.sof

.................\mem_cof.tan.rpt

.................\mem_cof.tan.summary

.................\mem_cof.v

.................\mem_cof_assignment_defaults.qdf

.................\mem_cof_nativelink_simulation.rpt

.................\simulation\modelsim\altera_mf.v

.................\..........\........\cyclone_atoms.v

.................\..........\........\mem_cof.sft

.................\..........\........\mem_cof.vo

.................\..........\........\mem_cof_modelsim.xrf

.................\..........\........\mem_cof_run_msim_rtl_verilog.do

.................\..........\........\mem_cof_run_msim_rtl_verilog.do.bak1

.................\..........\........\mem_cof_v.sdo

.................\..........\........\modelsim.ini

.................\..........\........\msim_transcript

.................\..........\........\rtl_work\mem_cof\verilog.prw

.................\..........\........\........\.......\verilog.psm

.................\..........\........\........\.......\_primary.dat

.................\..........\........\........\.......\_primary.dbs

.................\..........\........\........\.......\_primary.vhd

.................\..........\........\........\sys_ram\verilog.prw

.................\..........\........\........\.......\verilog.psm

.................\..........\........\........\.......\_primary.dat

.................\..........\........\........\.......\_primary.dbs

.................\..........\........\........\.......\_primary.vhd

.................\..........\........\........\tb_m4kram\verilog.prw

.................\..........\........\........\.........\verilog.psm

.................\..........\........\........\.........\_primary.dat

.................\..........\........\........\.........\_primary.dbs

.................\..........\........\........\.........\_primary.vhd

.................\..........\........\........\_info

.................\..........\........\........\_vmake

.................\..........\........\tb_m4kram.v

.................\..........\........\vsim.wlf

.................\..........\sim_prj\altera_mf.v

.................\..........\.......\cyclone\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm

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