文件名称:VITERBI_DECODER
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Verilog语言描述的应用于TD-SCDMA中的viterbi译码器rate_1-2_Viterbi_decoder-Applied in TD-SCDMA Verilog language descr iption of the viterbi decoder rate_1-2_Viterbi_decoder
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下载文件列表
Verilog_TD-SCDMA_Viterbi_decoder\sim\modelsim\do.txt
................................\...\icarus\block.list
................................\...\......\compile.bat
................................\...\......\gtk.bat
................................\...\......\run_random_data.bat
................................\doc\interface define.txt
................................\...\Specification.pdf
................................\bench\verilog\test_random_data.v
................................\.....\.......\test_fix_data.v
................................\rtl\verilog\butfly2.v
................................\...\.......\acs2.v
................................\...\.......\brameter2.v
................................\...\.......\delayT.v
................................\...\.......\glb_def.v
................................\...\.......\ctrl.v
................................\...\.......\centrofilo.v
................................\...\.......\dirtraback.v
................................\...\.......\decoder.v
................................\...\.......\tbdir_mod.v
................................\...\.......\pe.v
................................\...\.......\smu.v
................................\...\.......\virtual_mem.v
................................\...\.......\vit.v
................................\...\.......\encoder.v
................................\sim\modelsim
................................\...\icarus
................................\bench\verilog
................................\rtl\verilog
................................\sim
................................\doc
................................\bench
................................\rtl
Verilog_TD-SCDMA_Viterbi_decoder