文件名称:lab4
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s the design and simulation of a simple traffic light controller:
The controller consists of a clock divider block, two sequential circuits: a timing counter
and a signal generator (state generator), and a decoder. The counter is used to define a
fundamental timing signal (sw_out) that drives the signal generator (state-machine).
The signal generator generates the signals that control the traffic lights (state)
The controller consists of a clock divider block, two sequential circuits: a timing counter
and a signal generator (state generator), and a decoder. The counter is used to define a
fundamental timing signal (sw_out) that drives the signal generator (state-machine).
The signal generator generates the signals that control the traffic lights (state)
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下载文件列表
test
....\.lso
....\Capture.PNG
....\Capture1.PNG
....\Capture2.PNG
....\Capture3.PNG
....\clock.vhd
....\clocktest.ant
....\clocktest.jhd
....\clocktest.tbw
....\clocktest.xwv
....\clocktest.xwv_bak
....\clocktest_beh.prj
....\clocktest_isim_beh.exe
....\clocktest_isim_beh.wfs
....\clock_summary.html
....\counter.vhd
....\countertest.ant
....\countertest.jhd
....\countertest.tbw
....\countertest.xwv
....\countertest.xwv_bak
....\countertest_beh.prj
....\countertest_bencher.prj
....\countertest_isim_beh.exe
....\countertest_isim_beh.wfs
....\counter_summary.html
....\decoder.vhd
....\decodertest.ant
....\decodertest.jhd
....\decodertest.tbw
....\decodertest.vhw
....\decodertest.xwv
....\decodertest.xwv_bak
....\decodertest_beh.prj
....\decodertest_bencher.prj
....\decodertest_isim_beh.exe
....\decodertest_isim_beh.wfs
....\fsmtest.ant
....\fsmtest.jhd
....\fsmtest.tbw
....\fsmtest.xwv
....\fsmtest.xwv_bak
....\fsmtest_beh.prj
....\fsmtest_bencher.prj
....\fsmtest_isim_beh.exe
....\fsmtest_isim_beh.wfs
....\fuse.log
....\isim
....\....\isim.tmp_save
....\....\.............\_1
....\....\isimcrash.log
....\....\simulate_dofile.log
....\....\simulate_dofile.log_back
....\....\work
....\....\....\clock.vdb
....\....\....\clocktest.vdb
....\....\....\counter.vdb
....\....\....\countertest.vdb
....\....\....\decoder.vdb
....\....\....\decodertest.vdb
....\....\....\fsmtest.vdb
....\....\....\state_machine.vdb
....\....\_tmp
....\....\....\ieee
....\....\....\....\p_0017514958.didat
....\....\....\....\p_0774719531.didat
....\....\....\....\p_1242562249.didat
....\....\....\....\p_1367372525.didat
....\....\....\....\p_2592010699.didat
....\....\....\....\p_2717149903.didat
....\....\....\....\p_3039841270.didat
....\....\....\....\p_3499444699.didat
....\....\....\....\p_3564397177.didat
....\....\....\....\p_3620187407.didat
....\....\....\....\p_3972351953.didat
....\....\....\....\p_4165608084.didat
....\....\....\std
....\....\....\...\textio.didat
....\....\....\work
....\....\....\....\a_0213060440_3212880686.c
....\....\....\....\a_0213060440_3212880686.didat
....\....\....\....\a_0213060440_3212880686.nt.obj
....\....\....\....\a_0955132626_0230731466.c
....\....\....\....\a_0955132626_0230731466.didat
....\....\....\....\a_0955132626_0230731466.nt.obj
....\....\....\....\a_2263464102_3212880686.c
....\....\....\....\a_2263464102_3212880686.didat
....\....\....\....\a_2263464102_3212880686.nt.obj
....\....\....\....\a_2409194749_0230731466.c
....\....\....\....\a_2409194749_0230731466.didat
....\....\....\....\a_2409194749_0230731466.nt.obj
....\....\....\....\a_2577335280_3212880686.c
....\....\....\....\a_2577335280_3212880686.didat
....\....\....\....\a_2577335280_3212880686.nt.obj
....\....\....\....\a_2857244794_0230731466.c
....\....\....\....\a_2857244794_0230731466.didat
....\....\....\....\a_2857244794_0230731466.nt.obj
....\....\....\....\a_3308144156_0230731466.c
....\....\....\....\a_3308144156_0230731466.didat