文件名称:vga
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vga
This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.
This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.
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下载文件列表
VGA.VHD
VGA.VHD.bak
VGA_Project
...........\auto_project.ipf
...........\auto_project_xdb
...........\................\tmp
...........\impact.xsl
...........\impact_impact.xwbt
...........\iseconfig
...........\.........\VGA.xreport
...........\.........\VGA_Project.projectmgr
...........\usage_statistics_webtalk.html
...........\vga.bgn
...........\vga.bit
...........\VGA.bld
...........\VGA.cmd_log
...........\vga.drc
...........\VGA.lso
...........\VGA.ncd
...........\VGA.ngc
...........\VGA.ngd
...........\VGA.ngr
...........\VGA.pad
...........\VGA.par
...........\VGA.pcf
...........\VGA.prj
...........\VGA.ptwx
...........\VGA.stx
...........\VGA.syr
...........\VGA.twr
...........\VGA.twx
...........\VGA.unroutes
...........\VGA.ut
...........\VGA.xpi
...........\VGA.xst
...........\VGA_bitgen.xwbt
...........\VGA_envsettings.html
...........\VGA_guide.ncd
...........\VGA_map.map
...........\VGA_map.mrp
...........\VGA_map.ncd
...........\VGA_map.ngm
...........\VGA_map.xrpt
...........\VGA_ngdbuild.xrpt
...........\VGA_pad.csv
...........\VGA_pad.txt
...........\VGA_par.xrpt
...........\VGA_Project.gise
...........\VGA_Project.xise
...........\VGA_summary.html
...........\VGA_summary.xml
...........\VGA_usage.xml
...........\VGA_vhdl.prj
...........\VGA_xst.xrpt
...........\webtalk.log
...........\webtalk_impact.xml
...........\webtalk_pn.xml
...........\xlnx_auto_0_xdb
...........\...............\cst.xbcd
...........\xst
...........\...\dump.xst
...........\...\........\VGA.prj
...........\...\........\.......\ngx
...........\...\........\.......\...\notopt
...........\...\........\.......\...\opt
...........\...\projnav.tmp
...........\...\work
...........\...\....\hdllib.ref
...........\...\....\hdpdeps.ref
...........\...\....\sub00
...........\...\....\.....\vhpl00.vho
...........\...\....\.....\vhpl01.vho
...........\_impact.cmd
...........\_impact.log
...........\_ngo
...........\....\netlist.lst
...........\_xmsgs
...........\......\bitgen.xmsgs
...........\......\map.xmsgs
...........\......\ngdbuild.xmsgs
...........\......\par.xmsgs
...........\......\pn_parser.xmsgs
...........\......\trce.xmsgs
...........\......\xst.xmsgs
vga_tb.vhd
vga_tb.vhd.bak