文件名称:scr
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三段有限状态机编写-Three sections of a finite state machine to write
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scr
...\sim
...\...\vsim.wlf
...\...\work
...\...\work.cr.mti
...\...\work.mpf
...\...\....\three_seg_state_machine
...\...\....\.......................\verilog.asm
...\...\....\.......................\verilog.rw
...\...\....\.......................\_primary.dat
...\...\....\.......................\_primary.dbs
...\...\....\.......................\_primary.vhd
...\...\....\three_seg_state_machine_tb
...\...\....\..........................\verilog.asm
...\...\....\..........................\verilog.rw
...\...\....\..........................\_primary.dat
...\...\....\..........................\_primary.dbs
...\...\....\..........................\_primary.vhd
...\...\....\_info
...\...\....\_temp
...\...\....\.....\vlogw5snwy
...\...\....\.....\vlogwyxn9x
...\...\....\_vmake
...\three_seg_state_machine.v
...\three_seg_state_machine_tb.v