文件名称:adder
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实验要求：
（1）画出5位逐级进位和超前进位加法器的电路图，要求在图中表明输入、输出信号、中间信号等全部相关的信号，且信号命名应和图中的标注一一对应；
（2）不能使用课本中的FOR循环语句，VHDL的赋值语句应和电路图一一对应；
（3）VHDL代码和仿真波形要保存。
（4）关于超前进位加法器，可以参照课本P160设计。
（5） 要求提交设计报告，按照深大实验报告的标准格式，同时需要代码，仿真结果和综合电路图。 -The experimental requirements:
(1) to draw the 5 cascaded carry and circuit diagrams of carry look ahead adder, required to indicate signal input, output signal, the intermediate signal and all other related in the figure, and the signal should be named annotation and figure one one corresponding
(2) can not be used textbooks in the FOR loop statement, the assignment statement of VHDL should be and the circuit in figure one one correspond
(3) VHDL code and the simulation waveform to save.
(4) on the carry lookahead adder, can reference books P160 design.
(5) required to submit the design report, in accordance with the standard format deep experimental report, also need to code, the simulation results and the integrated circuit diagram.
（1）画出5位逐级进位和超前进位加法器的电路图，要求在图中表明输入、输出信号、中间信号等全部相关的信号，且信号命名应和图中的标注一一对应；
（2）不能使用课本中的FOR循环语句，VHDL的赋值语句应和电路图一一对应；
（3）VHDL代码和仿真波形要保存。
（4）关于超前进位加法器，可以参照课本P160设计。
（5） 要求提交设计报告，按照深大实验报告的标准格式，同时需要代码，仿真结果和综合电路图。 -The experimental requirements:
(1) to draw the 5 cascaded carry and circuit diagrams of carry look ahead adder, required to indicate signal input, output signal, the intermediate signal and all other related in the figure, and the signal should be named annotation and figure one one corresponding
(2) can not be used textbooks in the FOR loop statement, the assignment statement of VHDL should be and the circuit in figure one one correspond
(3) VHDL code and the simulation waveform to save.
(4) on the carry lookahead adder, can reference books P160 design.
(5) required to submit the design report, in accordance with the standard format deep experimental report, also need to code, the simulation results and the integrated circuit diagram.
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下载文件列表
加法器\CLA_Adder.png
......\CLA_Adder.txt
......\adder.txt
......\adder_cripple.png
......\adder_cripple.txt
......\zuoye.txt
加法器