文件名称:DE4_230_DDR2_UniPHY_QSYS
介绍说明－－下载内容均来自于网络，请自行研究使用
DE4系列开发板关于ddr2在Qsys系统搭建的实例，有一定参考价值，。-DE4 series development board on the DDR2 in the example of Qsys system, has a certain reference value,.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE4_230_DDR2_UniPHY_QSYS\.qsys_edit\filters.xml
........................\..........\preferences.xml
........................\.qsys_edit
........................\DE4_DDR2.cdf
........................\DE4_DDR2.done
........................\DE4_DDR2.dpf
........................\DE4_DDR2.fit.smsg
........................\DE4_DDR2.fit.summary
........................\DE4_DDR2.jdi
........................\DE4_DDR2.map.smsg
........................\DE4_DDR2.map.summary
........................\DE4_DDR2.pin
........................\DE4_DDR2.qpf
........................\DE4_DDR2.qsf
........................\DE4_DDR2.sdc
........................\DE4_DDR2.sof
........................\DE4_DDR2.sta.summary
........................\DE4_DDR2.v
........................\....QSYS\synthesis\DE4_QSYS.qip
........................\........\.........\DE4_QSYS.v
........................\........\.........\submodules\altdq_dqs2_ddio_3reg_stratixiv.sv
........................\........\.........\..........\altera_avalon_dc_fifo.v
........................\........\.........\..........\altera_avalon_mm_clock_crossing_bridge.v
........................\........\.........\..........\altera_avalon_sc_fifo.v
........................\........\.........\..........\altera_avalon_st_clock_crosser.v
........................\........\.........\..........\altera_avalon_st_handshake_clock_crosser.v
........................\........\.........\..........\altera_avalon_st_pipeline_base.v
........................\........\.........\..........\altera_dcfifo_synchronizer_bundle.v
........................\........\.........\..........\altera_irq_clock_crosser.sv
........................\........\.........\..........\altera_merlin_arbitrator.sv
........................\........\.........\..........\altera_merlin_burst_adapter.sv
........................\........\.........\..........\altera_merlin_burst_uncompressor.sv
........................\........\.........\..........\altera_merlin_master_agent.sv
........................\........\.........\..........\altera_merlin_master_translator.sv
........................\........\.........\..........\altera_merlin_slave_agent.sv
........................\........\.........\..........\altera_merlin_slave_translator.sv
........................\........\.........\..........\altera_merlin_traffic_limiter.sv
........................\........\.........\..........\altera_merlin_width_adapter.sv
........................\........\.........\..........\altera_reset_controller.sdc
........................\........\.........\..........\altera_reset_controller.v
........................\........\.........\..........\altera_reset_synchronizer.v
........................\........\.........\..........\alt_mem_ddrx_addr_cmd.v
........................\........\.........\..........\alt_mem_ddrx_addr_cmd_wrap.v
........................\........\.........\..........\alt_mem_ddrx_arbiter.v
........................\........\.........\..........\alt_mem_ddrx_buffer.v
........................\........\.........\..........\alt_mem_ddrx_buffer_manager.v
........................\........\.........\..........\alt_mem_ddrx_burst_gen.v
........................\........\.........\..........\alt_mem_ddrx_burst_tracking.v
........................\........\.........\..........\alt_mem_ddrx_cmd_gen.v
........................\........\.........\..........\alt_mem_ddrx_controller.v
........................\........\.........\..........\alt_mem_ddrx_controller_st_top.v
........................\........\.........\..........\alt_mem_ddrx_csr.v
........................\........\.........\..........\alt_mem_ddrx_dataid_manager.v
........................\........\.........\..........\alt_mem_ddrx_ddr2_odt_gen.v
........................\........\.........\..........\alt_mem_ddrx_ddr3_odt_gen.v
........................\........\.........\..........\alt_mem_ddrx_define.iv
........................\........\.........\..........\alt_mem_ddrx_ecc_decoder.v
........................\........\.........\..........\alt_mem_ddrx_ecc_decoder_32_syn.v
........................\.......