文件名称:plj
介绍说明－－下载内容均来自于网络，请自行研究使用
时钟分频器原理与实现，计数跳变的频率和加减模式可实时变化，通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nano experiments. Counting frequency, subtraction selection and initialization by a toggle switch panel and Reset buttons to achieve.
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下载文件列表
plj\b2a.Vhd
...\b2a_plj.SchLib
...\banshangtu.SchDoc
...\control_plj.SchLib
...\dinlatch_plj.SchLib
...\FPGA_Project1.PrjFpg
...\FPGA_Project1.SO
...\FPGA_Project2.PrjFpg
...\FPGA_Project2.SO
...\FPGA_Project3.PrjFpg
...\FPGA_Project3.SO
...\FPGA_Project4.PrjFpg
...\FPGA_Project4.PrjFpgStructure
...\FPGA_Project4.SO
...\FPGA_Project5.PrjFpg
...\FPGA_Project6.PrjFpg
...\FPGA_Project6.PrjFpgStructure
...\History\banshangtu.~(1).SchDoc.Zip
...\.......\FPGA_Project1.~(1).PrjFpg.Zip
...\.......\FPGA_Project1.~(2).PrjFpg.Zip
...\.......\FPGA_Project2.~(1).PrjFpg.Zip
...\.......\FPGA_Project2.~(1).SO.Zip
...\.......\FPGA_Project2.~(10).PrjFpg.Zip
...\.......\FPGA_Project2.~(11).PrjFpg.Zip
...\.......\FPGA_Project2.~(12).PrjFpg.Zip
...\.......\FPGA_Project2.~(2).PrjFpg.Zip
...\.......\FPGA_Project2.~(2).SO.Zip
...\.......\FPGA_Project2.~(3).PrjFpg.Zip
...\.......\FPGA_Project2.~(4).PrjFpg.Zip
...\.......\FPGA_Project2.~(5).PrjFpg.Zip
...\.......\FPGA_Project2.~(6).PrjFpg.Zip
...\.......\FPGA_Project2.~(7).PrjFpg.Zip
...\.......\FPGA_Project2.~(8).PrjFpg.Zip
...\.......\FPGA_Project2.~(9).PrjFpg.Zip
...\.......\FPGA_Project3.~(1).PrjFpg.Zip
...\.......\FPGA_Project3.~(2).PrjFpg.Zip
...\.......\FPGA_Project4.~(1).PrjFpg.Zip
...\.......\FPGA_Project4.~(2).PrjFpg.Zip
...\.......\FPGA_Project4.~(3).PrjFpg.Zip
...\.......\FPGA_Project4.~(4).PrjFpg.Zip
...\.......\FPGA_Project5.~(1).PrjFpg.Zip
...\.......\FPGA_Project5.~(2).PrjFpg.Zip
...\.......\FPGA_Project6.~(1).PrjFpg.Zip
...\.......\pinlvji.~(1).PrjFpg.Zip
...\.......\pinlvji.~(2).PrjFpg.Zip
...\.......\ProjectOutputs\Sheet2.~(1).VHD.Zip
...\.......\..............\Sheet3.~(1).VHD.Zip
...\.......\..............\Sheet3.~(2).VHD.Zip
...\.......\..............\Sheet3.~(3).VHD.Zip
...\.......\Sheet1.~(1).SchDoc.Zip
...\.......\Sheet1.~(2).SchDoc.Zip
...\.......\Sheet1.~(3).SchDoc.Zip
...\.......\Sheet1.~(4).SchDoc.Zip
...\.......\Sheet1.~(5).SchDoc.Zip
...\.......\Sheet1.~(6).SchDoc.Zip
...\.......\Sheet2.~(1).SchDoc.Zip
...\.......\Sheet2.~(2).SchDoc.Zip
...\.......\Sheet2.~(3).SchDoc.Zip
...\.......\Sheet3.~(1).SchDoc.Zip
...\.......\Sheet3.~(2).SchDoc.Zip
...\.......\Sheet3.~(3).SchDoc.Zip
...\.......\Test_cnt10.~(1).VHDTST.Zip
...\.......\Test_cnt10.~(10).VHDTST.Zip
...\.......\Test_cnt10.~(11).VHDTST.Zip
...\.......\Test_cnt10.~(2).VHDTST.Zip
...\.......\Test_cnt10.~(3).VHDTST.Zip
...\.......\Test_cnt10.~(4).VHDTST.Zip
...\.......\Test_cnt10.~(5).VHDTST.Zip
...\.......\Test_cnt10.~(6).VHDTST.Zip
...\.......\Test_cnt10.~(7).VHDTST.Zip
...\.......\Test_cnt10.~(8).VHDTST.Zip
...\.......\Test_cnt10.~(9).VHDTST.Zip
...\.......\Test_fpga_project4.~(1).VHDTST.Zip
...\.......\VHDL2.~(1).Vhd.Zip
...\.......\VHDL2.~(2).Vhd.Zip
...\.......\VHDL2.~(3).Vhd.Zip
...\.......\VHDL2.~(4).Vhd.Zip
...\.......\VHDL3.~(1).Vhd.Zip
...\.......\VHDL3.~(2).Vhd.Zip
...\.......\VHDL4.~(1).Vhd.Zip
...\.......\VHDL4.~(2).Vhd.Zip
...\.......\VHDL4.~(3).Vhd.Zip
...\jishuqi_plj.SchLib
...\lcd_scan_plj.SchLib
...\pinlvji.PrjFpg
...\pinlvji.PrjFpgStructure
...\Project Logs for FPGA_Project4\Sheet1 SCH ECO 2013-5-22 19-51-04.LOG
...\.................pinlvji\banshangtu SCH ECO 2013-5-26 20-47-55.LOG
...\........................\Sheet1 SCH ECO 2013-5-26 20-32-24.LOG
...\........................\Sheet1 SCH ECO 2013-5-26 20-46-06.LOG
...\.......Outputs\banshangtu.VHD
...\..............\FPGA_Project1_BUILT_IN_ALDEC\FPGA_Project1.top
...\..............\............2_BUILT_IN_ALDEC\FPGA_Project2.top
...\..............\............3_BUILT_IN_ALDEC\FPGA_Project3.top
...\..............\............4_BUILT_IN_ALDEC\FPGA_Project4\0FPGA_Project4.mgf
...\..............\............................\.............\1FPGA_Project4.mgf
...\..............\............................\.............\3FPGA_Project4.mgf
...\..............\............................\.............\elaboration.log
...\..............\............................\.............\FPGA_Project4.lib
...\..............\............................\FPGA_Project4.top