文件名称:div_3

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2015-01-13
  • 文件大小:
  • 4mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用Verilog实现时钟三分频,该代码包含完整的工程文件,可直接运行。-The realization of clock frequency of three Verilog, the code contains the complete engineering documents, can be directly run.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





div_3\db\div_3.amm.cdb

.....\..\div_3.asm.qmsg

.....\..\div_3.asm.rdb

.....\..\div_3.asm_labs.ddb

.....\..\div_3.cbx.xml

.....\..\div_3.cmp.bpm

.....\..\div_3.cmp.cdb

.....\..\div_3.cmp.hdb

.....\..\div_3.cmp.kpt

.....\..\div_3.cmp.logdb

.....\..\div_3.cmp.rdb

.....\..\div_3.cmp_merge.kpt

.....\..\div_3.db_info

.....\..\div_3.eda.qmsg

.....\..\div_3.fit.qmsg

.....\..\div_3.hier_info

.....\..\div_3.hif

.....\..\div_3.idb.cdb

.....\..\div_3.lpc.html

.....\..\div_3.lpc.rdb

.....\..\div_3.lpc.txt

.....\..\div_3.map.bpm

.....\..\div_3.map.cdb

.....\..\div_3.map.hdb

.....\..\div_3.map.kpt

.....\..\div_3.map.logdb

.....\..\div_3.map.qmsg

.....\..\div_3.map_bb.cdb

.....\..\div_3.map_bb.hdb

.....\..\div_3.map_bb.logdb

.....\..\div_3.pre_map.cdb

.....\..\div_3.pre_map.hdb

.....\..\div_3.rtlv.hdb

.....\..\div_3.rtlv_sg.cdb

.....\..\div_3.rtlv_sg_swap.cdb

.....\..\div_3.sgdiff.cdb

.....\..\div_3.sgdiff.hdb

.....\..\div_3.sld_design_entry.sci

.....\..\div_3.sld_design_entry_dsc.sci

.....\..\div_3.smart_action.txt

.....\..\div_3.sta.qmsg

.....\..\div_3.sta.rdb

.....\..\div_3.sta_cmp.6_slow_1200mv_85c.tdb

.....\..\div_3.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd

.....\..\div_3.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd

.....\..\div_3.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd

.....\..\div_3.syn_hier_info

.....\..\div_3.tiscmp.fast_1200mv_0c.ddb

.....\..\div_3.tiscmp.slow_1200mv_0c.ddb

.....\..\div_3.tiscmp.slow_1200mv_85c.ddb

.....\..\div_3.tis_db_list.ddb

.....\..\div_3.tmw_info

.....\..\logic_util_heursitic.dat

.....\..\prev_cmp_div_3.qmsg

.....\div_3.asm.rpt

.....\div_3.done

.....\div_3.eda.rpt

.....\div_3.fit.rpt

.....\div_3.fit.smsg

.....\div_3.fit.summary

.....\div_3.flow.rpt

.....\div_3.map.rpt

.....\div_3.map.summary

.....\div_3.pin

.....\div_3.qpf

.....\div_3.qsf

.....\div_3.sof

.....\div_3.sta.rpt

.....\div_3.sta.summary

.....\div_3.v

.....\div_3.v.bak

.....\div_3_nativelink_simulation.rpt

.....\incremental_db\compiled_partitions\div_3.db_info

.....\..............\...................\div_3.root_partition.cmp.cbp

.....\..............\...................\div_3.root_partition.cmp.cdb

.....\..............\...................\div_3.root_partition.cmp.dfp

.....\..............\...................\div_3.root_partition.cmp.hdb

.....\..............\...................\div_3.root_partition.cmp.kpt

.....\..............\...................\div_3.root_partition.cmp.logdb

.....\..............\...................\div_3.root_partition.cmp.rcfdb

.....\..............\...................\div_3.root_partition.cmp.re.rcfdb

.....\..............\...................\div_3.root_partition.map.cbp

.....\..............\...................\div_3.root_partition.map.cdb

.....\..............\...................\div_3.root_partition.map.dpi

.....\..............\...................\div_3.root_partition.map.hdb

.....\..............\...................\div_3.root_partition.map.kpt

.....\..............\README

.....\..............\compiled_partitions

.....\db

.....\incremental_db

div_3

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