文件名称:booth_multiplie_module
- 所属分类：
- 其他小程序
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2014-12-17
- 文件大小：
- 184kb
- 下载次数：
- 0次
- 提 供 者：
- cheng*****
- 相关连接：
- 无
- 下载说明：
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利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
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下载文件列表
Experiment03\booth_multiplier_module.asm.rpt
............\booth_multiplier_module.done
............\booth_multiplier_module.eda.rpt
............\booth_multiplier_module.fit.rpt
............\booth_multiplier_module.fit.smsg
............\booth_multiplier_module.fit.summary
............\booth_multiplier_module.flow.rpt
............\booth_multiplier_module.map.rpt
............\booth_multiplier_module.map.summary
............\booth_multiplier_module.pin
............\booth_multiplier_module.pof
............\booth_multiplier_module.qpf
............\booth_multiplier_module.qsf
............\booth_multiplier_module.qws
............\booth_multiplier_module.sof
............\booth_multiplier_module.sta.rpt
............\booth_multiplier_module.sta.summary
............\booth_multiplier_module.tan.rpt
............\booth_multiplier_module.tan.summary
............\booth_multiplier_module.vt
............\booth_multiplier_module_assignment_defaults.qdf
............\booth_multiplier_module_nativelink_simulation.rpt
............\booth_multiplie_module.v
............\booth_multiplie_module.v.bak
............\db\booth_multiplier_module.db_info
............\..\booth_multiplier_module.eco.cdb
............\..\booth_multiplier_module.sld_design_entry.sci
............\..\logic_util_heursitic.dat
............\..\prev_cmp_booth_multiplier_module.qmsg
............\incremental_db\compiled_partitions\booth_multiplier_module.root_partition.cmp.cdb
............\..............\...................\booth_multiplier_module.root_partition.cmp.dfp
............\..............\...................\booth_multiplier_module.root_partition.cmp.hdb
............\..............\...................\booth_multiplier_module.root_partition.cmp.kpt
............\..............\...................\booth_multiplier_module.root_partition.cmp.logdb
............\..............\...................\booth_multiplier_module.root_partition.cmp.rcfdb
............\..............\...................\booth_multiplier_module.root_partition.cmp.re.rcfdb
............\..............\...................\booth_multiplier_module.root_partition.map.cdb
............\..............\...................\booth_multiplier_module.root_partition.map.dpi
............\..............\...................\booth_multiplier_module.root_partition.map.hdb
............\..............\...................\booth_multiplier_module.root_partition.map.kpt
............\..............\README
............\simulation\modelsim\booth_multiplier_module.sft
............\..........\........\booth_multiplier_module.vo
............\..........\........\booth_multiplier_module.vt
............\..........\........\booth_multiplier_module.vt.bak
............\..........\........\booth_multiplier_module_fast.vo
............\..........\........\booth_multiplier_module_modelsim.xrf
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak1
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak2
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak3
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak4
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak5
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak6
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak7
............\..........\........\booth_multiplier_module_run_msim_rtl_verilog.do.bak8
............\..........\........\booth_multiplier_module_v.sdo
............\..........\........\booth_multiplier_module_v_fast.sdo
............\..........\........\modelsim.ini
............\..........\........\msim_transcript
............\..........\........\rtl_work\booth_multiplier_module\verilog.prw
............\..........\........\........\.......................\verilog.psm
............\..........\........\........\...