文件名称:verilog-code-for-8bit-multiplier-using-vedic-algo
介绍说明－－下载内容均来自于网络，请自行研究使用
The vedic multiplier is used perform 16 bit multiplication using urdhva tiryakbhyam sutra. this produces the results with high speed and utilizes low power which is most efficient for the real time processors.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog code for 8bit multiplier using vedic algoritham.docx