文件名称:06662257
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在这项工作中,我们提出一个基于混沌的集成 抖动升压电路用于多个振荡器抽样真的 随机数发生器的架构。多个环形振荡器 真正的随机数生成器需要大量 戒指的积累内在抖动的逆变器 有用的水平。因此,他们占领大的硅区域和消费 大量的权力。该电路提供 另一种方法推动使用混乱的抖动 动态生成的两个环形振荡器的非线性耦合 需要更少的组件的数量。的简单性 提出了电路提供高集成和内在潜力 面积和功耗低等优点。混沌动力学 研究了电路的使用数值和电路 模拟。测量测试芯片实现的结果 250纳米CMOS技术-In this work, we present a chaos based integrated
jitter booster circuit for use in multiple oscillator sampling true
random number generator architecture. Multiple ring oscillator
based true random number generators need significant number
of rings for accumulating the intrinsic jitter of inverters to a
useful level. Thus, they occupy large silicon area and consume
considerable amount of power. The proposed circuit offers
an alternative approach for boosting jitter using the chaotic
dynamics generated by non-linear coupling of two ring oscillators
that require fewer number of components. The simplicity of the
proposed circuit offers high integration potential with inherent
low area and power consumption advantages. Chaotic dynamics
of the circuit was studied using both numerical and circuit
simulations. Measurement results of the test chip implemented at
250nm CMOS technology node confirmed chaotic behavior and
jitter boosting capability. To the very best of our knowled
jitter booster circuit for use in multiple oscillator sampling true
random number generator architecture. Multiple ring oscillator
based true random number generators need significant number
of rings for accumulating the intrinsic jitter of inverters to a
useful level. Thus, they occupy large silicon area and consume
considerable amount of power. The proposed circuit offers
an alternative approach for boosting jitter using the chaotic
dynamics generated by non-linear coupling of two ring oscillators
that require fewer number of components. The simplicity of the
proposed circuit offers high integration potential with inherent
low area and power consumption advantages. Chaotic dynamics
of the circuit was studied using both numerical and circuit
simulations. Measurement results of the test chip implemented at
250nm CMOS technology node confirmed chaotic behavior and
jitter boosting capability. To the very best of our knowled
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