文件名称:quanjiaqi
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使用verilog HDL实现全加器的功能-Use verilog HDL to achieve full adder function
(系统自动生成,下载前可以参看下载内容)
下载文件列表
quanjiaqi\jishiqi.v
.........\jishiqi.v.bak
.........\quanjia1.v
.........\quanjia1.v.bak
.........\quanjia3.v
.........\quanjia3.v.bak
.........\quanjiaqi.cr.mti
.........\quanjiaqi.mpf
.........\transcript
.........\t_quanjia3.v
.........\t_quanjia3.v.bak
.........\vsim.wlf
.........\work\@c@n@t10\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\quanjia1\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\.......3\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\t_quanjia3\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\_info
.........\....\@c@n@t10
.........\....\quanjia1
.........\....\quanjia3
.........\....\t_quanjia3
.........\work
quanjiaqi