文件名称:digital-clock
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用FPGA实现数字钟功能，用VHDL语言编写，含有课程设计报告-FPGA digital clock
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下载文件列表
数字钟1
.......\多功能数字电子钟_VHDL.doc
.......\数字逻辑课程设计.doc
.......\源文件
.......\......\bell.sof
.......\......\bell.vhd
.......\......\bridge.sof
.......\......\bridge.vhd
.......\......\comp.sof
.......\......\comp.vhd
.......\......\controller.scf
.......\......\controller.sof
.......\......\controller.vhd
.......\......\count_16.sof
.......\......\count_8.sof
.......\......\count_8.vhd
.......\......\decode8.sof
.......\......\decode8.vhd
.......\......\dshi.vhd
.......\......\dx.sof
.......\......\fenp.sof
.......\......\fenpin.scf
.......\......\fenpin.vhd
.......\......\h24.scf
.......\......\h24.vhd
.......\......\jishi.vhd
.......\......\kong.sof
.......\......\kong.vhd
.......\......\m60.scf
.......\......\m60.sof
.......\......\m60.vhd
.......\......\mux2.vhd
.......\......\mux2_1.scf
.......\......\mux2_1.sof
.......\......\mux2_1.vhd
.......\......\mux8_1.sof
.......\......\mux8_1.vhd
.......\......\s60.scf
.......\......\s60.sof
.......\......\s60.vhd
.......\......\showconl.sof
.......\......\showconl.vhd
.......\......\shuzizhong.gdf
.......\......\shuzizhong.sof