文件名称:sobel
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在FPGA中,采用verilog HDL语言实现图像处理算法sobel,仿真实验通过-In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment
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下载文件列表
sobel
.....\abs.bmm
.....\data3by3.v
.....\data3by3_compute.gise
.....\data3by3_compute.xise
.....\data_grads.v
.....\fuse.log
.....\fuse.xmsgs
.....\fuseRelaunch.cmd
.....\generate_data3by3.v
.....\generate_data3by3_summary.html
.....\Grads.bld
.....\Grads.cmd_log
.....\Grads.lso
.....\Grads.ncd
.....\Grads.ngc
.....\Grads.ngd
.....\Grads.ngr
.....\Grads.pad
.....\Grads.par
.....\Grads.pcf
.....\Grads.prj
.....\Grads.ptwx
.....\Grads.stx
.....\Grads.syr
.....\Grads.twr
.....\Grads.twx
.....\Grads.unroutes
.....\grads.v
.....\Grads.xpi
.....\Grads.xst
.....\Grads_envsettings.html
.....\Grads_guide.ncd
.....\Grads_map.map
.....\Grads_map.mrp
.....\Grads_map.ncd
.....\Grads_map.ngm
.....\Grads_map.xrpt
.....\Grads_ngdbuild.xrpt
.....\Grads_pad.csv
.....\Grads_pad.txt
.....\Grads_par.xrpt
.....\Grads_summary.html
.....\Grads_summary.xml
.....\grads_test.v
.....\grads_test_beh.prj
.....\grads_test_isim_beh.exe
.....\grads_test_isim_beh.wdb
.....\grads_test_stx_beh.prj
.....\Grads_usage.xml
.....\Grads_xst.xrpt
.....\Gx_grad.v
.....\Gy_grad.v
.....\ipcore_dir
.....\..........\add
.....\..........\add.asy
.....\..........\add.gise
.....\..........\add.ncf
.....\..........\add.ngc
.....\..........\add.sym
.....\..........\add.v
.....\..........\add.veo
.....\..........\add.xco
.....\..........\add.xise
.....\..........\...\doc
.....\..........\...\...\c_addsub_v11_0_readme.txt
.....\..........\...\...\c_addsub_v11_0_vinfo.html
.....\..........\...\...\ds214_addsub.pdf
.....\..........\add_18bit
.....\..........\add_18bit.asy
.....\..........\add_18bit.gise
.....\..........\add_18bit.ncf
.....\..........\add_18bit.ngc
.....\..........\add_18bit.sym
.....\..........\add_18bit.v
.....\..........\add_18bit.veo
.....\..........\add_18bit.xco
.....\..........\add_18bit.xise
.....\..........\.........\doc
.....\..........\.........\...\c_addsub_v11_0_readme.txt
.....\..........\.........\...\c_addsub_v11_0_vinfo.html
.....\..........\.........\...\ds214_addsub.pdf
.....\..........\add_18bit_flist.txt
.....\..........\add_18bit_xmdf.tcl
.....\..........\add_9bit
.....\..........\add_9bit.asy
.....\..........\add_9bit.gise
.....\..........\add_9bit.ncf
.....\..........\add_9bit.ngc
.....\..........\add_9bit.sym
.....\..........\add_9bit.v
.....\..........\add_9bit.veo
.....\..........\add_9bit.xco
.....\..........\add_9bit.xise
.....\..........\........\doc
.....\..........\........\...\c_addsub_v11_0_readme.txt
.....\..........\........\...\c_addsub_v11_0_vinfo.html
.....\..........\........\...\ds214_addsub.pdf
.....\..........\add_9bit_flist.txt
.....\..........\add_9bit_xmdf.tcl