文件名称:I2C-protocol-implement-Sampling
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工程文件中代码是通过I2C协议来实现采样功能的实现-Engineering document code is through the I2C protocol to achieve the realization of the function of sampling
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下载文件列表
I2C protocol implement Sampling\I2C协议实现 Sample\I2C\automake.log
...............................\..................\...\coregen.log
...............................\..................\...\coregen.prj
...............................\..................\...\I2C.dhp
...............................\..................\...\I2C.npl
...............................\..................\...\i2c_master_bit_ctrl.cmd_log
...............................\..................\...\i2c_master_bit_ctrl.lso
...............................\..................\...\i2c_master_bit_ctrl.ngc
...............................\..................\...\i2c_master_bit_ctrl.ngr
...............................\..................\...\i2c_master_bit_ctrl.prj
...............................\..................\...\i2c_master_bit_ctrl.stx
...............................\..................\...\i2c_master_bit_ctrl.syr
...............................\..................\...\i2c_master_bit_ctrl.v
...............................\..................\...\i2c_master_bit_ctrl.v.bak
...............................\..................\...\i2c_master_bit_ctrl_vhdl.prj
...............................\..................\...\i2c_master_byte_ctrl.cmd_log
...............................\..................\...\i2c_master_byte_ctrl.lso
...............................\..................\...\i2c_master_byte_ctrl.ngc
...............................\..................\...\i2c_master_byte_ctrl.ngr
...............................\..................\...\i2c_master_byte_ctrl.prj
...............................\..................\...\i2c_master_byte_ctrl.stx
...............................\..................\...\i2c_master_byte_ctrl.syr
...............................\..................\...\i2c_master_byte_ctrl.v
...............................\..................\...\i2c_master_byte_ctrl.v.bak
...............................\..................\...\i2c_master_byte_ctrl_vhdl.prj
...............................\..................\...\i2c_master_defines.v
...............................\..................\...\i2c_master_defines.v.bak
...............................\..................\...\i2c_master_top.cmd_log
...............................\..................\...\i2c_master_top.lso
...............................\..................\...\i2c_master_top.ngc
...............................\..................\...\i2c_master_top.ngr
...............................\..................\...\i2c_master_top.prj
...............................\..................\...\i2c_master_top.stx
...............................\..................\...\i2c_master_top.syr
...............................\..................\...\i2c_master_top.v
...............................\..................\...\i2c_master_top.v.bak
...............................\..................\...\i2c_master_top_vhdl.prj
...............................\..................\...\i2c_slave_model.fdo
...............................\..................\...\i2c_slave_model.ndo
...............................\..................\...\i2c_slave_model.udo
...............................\..................\...\i2c_slave_model.v
...............................\..................\...\i2c_slave_model.v.bak
...............................\..................\...\prjname.lso
...............................\..................\...\timescale.v
...............................\..................\...\transcript
...............................\..................\...\tst_bench_top.v
...............................\..................\...\wb_master_model.v
...............................\..................\...\wb_master_model.v.bak
...............................\..................\...\.ork\glbl\verilog.asm
...............................\..................\...\....\....\_primary.dat
...............................\..................\...\....\....\_primary.vhd
...............................\..................\...\....\i2c_slave_model\verilog.asm
...............................\..................\...\....\...............\_primary.dat
...............................\.............