文件名称:I2C-code-Base-on--FPGA
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该工程文件中代码是用于实现基于FPGA的I2C的通信实验，可移植性强-The project file code is used to implement an FPGA-based I2C communication experiment, the portability
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I2C code Base on FPGA\bench\CVS\Entries
......................\.....\...\Repository
......................\.....\...\Root
......................\.....\verilog\CVS\Entries
......................\.....\.......\...\Repository
......................\.....\.......\...\Root
......................\.....\.......\i2c_slave_model.v
......................\.....\.......\i2c_slave_model.v.bak
......................\.....\.......\spi_slave_model.v
......................\.....\.......\spi_slave_model.v.bak
......................\.....\.......\tst_bench_top.v
......................\.....\.......\tst_bench_top.v.bak
......................\.....\.......\wb_master_model.v
......................\.....\.......\wb_master_model.v.bak
......................\CVS\Entries
......................\...\Repository
......................\...\Root
......................\doc\CVS\Entries
......................\...\...\Repository
......................\...\...\Root
......................\...\i2c_specs.pdf
......................\...\src\CVS\Entries
......................\...\...\...\Repository
......................\...\...\...\Root
......................\...\...\I2C_specs.doc
......................\rtl\CVS\Entries
......................\...\...\Repository
......................\...\...\Root
......................\...\verilog\CVS\Entries
......................\...\.......\...\Repository
......................\...\.......\...\Root
......................\...\.......\i2c_master_bit_ctrl.v
......................\...\.......\i2c_master_bit_ctrl.v.bak
......................\...\.......\i2c_master_byte_ctrl.v
......................\...\.......\i2c_master_byte_ctrl.v.bak
......................\...\.......\i2c_master_defines.v
......................\...\.......\i2c_master_top.v
......................\...\.......\i2c_master_top.v.bak
......................\...\.......\timescale.v
......................\...\.hdl\CVS\Entries
......................\...\....\...\Repository
......................\...\....\...\Root
......................\...\....\I2C.VHD
......................\...\....\i2c_master_bit_ctrl.vhd
......................\...\....\i2c_master_byte_ctrl.vhd
......................\...\....\i2c_master_top.vhd
......................\...\....\readme
......................\...\....\tst_ds1621.vhd
......................\sim\CVS\Entries
......................\...\...\Repository
......................\...\...\Root
......................\...\i2c.cr.mti
......................\...\i2c.mpf
......................\...\..._verilog\CVS\Entries
......................\...\...........\...\Repository
......................\...\...........\...\Root
......................\...\...........\run\bench.vcd
......................\...\...........\...\CVS\Entries
......................\...\...........\...\...\Repository
......................\...\...........\...\...\Root
......................\...\...........\...\INCA_libs\CVS\Entries
......................\...\...........\...\.........\...\Repository
......................\...\...........\...\.........\...\Root
......................\...\...........\...\ncverilog.key
......................\...\...........\...\ncverilog.log
......................\...\...........\...\run
......................\...\...........\...\waves\CVS\Entries
......................\...\...........\...\.....\...\Repository
......................\...\...........\...\.....\...\Root
......................\...\vsim.wlf
......................\...\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.asm
......................\...\....\............................\_primary.dat
......................\...\....\............................\_primary.vhd
......................\...\....\delay\verilog.asm
......................\...\....\.....\_primary.dat
......................\...\....\.....\_primary.vhd
......................\...\....\i2c_master_bit_ctrl\verilog.asm
......................\...\....\...................\_primary.dat
......................\...\....\...................\_primary.vhd
......................\...\....\............yte_ctrl\verilog.asm
......................\...\....\....